The article's title states that agentic AI is expected to increase CPU, memory and networking demands in data centers. The body explains that agentic workloads require more CPU capacity, persistent state management, high-speed storage and secure execution across cloud infrastructure. The source provides no specific figures, timeframe, involved companies, inventory or supply-demand conditions, and does not state a cause.
In November, AMD unveiled MEXT Predictive Memory Software, a flash-based, AI-powered predictive memory solution that could slash DRAM requirements by 20–75% across EPYC servers while easing costs and supply pressures with comparable performance; the rollout follows AMD's acquisition of MEXT in June. The cause lies in DRAM overprovisioning: enterprises often overprovision memory to prevent performance slowdowns; according to Wccftech, DRAM overprovisioning can reach 50% (half of allocated memory untouched by virtual machines), another 25% remains stranded within instances, and overall 50–80% of DRAM capacity may be underutilized as memory pages become inactive or 'cold'; DRAM reportedly accounts for as much as 75% of total server costs amid persistent supply shortages. MEXT shifts idle data to flash and uses AI to anticipate demand, moving data back to DRAM before applications need it to minimize latency. According to Wccftech, MEXT could effectively triple available memory capacity at a fraction of the cost of adding physical DRAM; AMD claims a 50/50 mix of DRAM and MEXT-enabled flash could boost performance per dollar by 90% in five-agent concurrent workflows and 70% in memory-intensive agent applications (AMD claims). AMD is already putting MEXT to work in its own IT infrastructure: an initial deployment across 145 servers is expected to avoid roughly $4.9 million in DRAM purchases, slashing memory expansion costs by 83% versus an equivalent DRAM-only upgrade (expected, not confirmed as achieved), and AMD aims to expand the rollout to 2,000 servers by 2027. AMD is also teaming up with Hewlett Packard Enterprise (HPE) to bring MEXT to enterprise customers, initially focusing on 'MEXT Ready' systems with ample CPU cores and NVMe expansion capacity. Separately, NVIDIA is taking a related, though distinct, approach in AI inference with its Context Memory Storage (CMX) platform, which adds a flash-based tier beneath GPU HBM and host DRAM for KV cache; according to Wccftech, CMX uses TLC flash connected to Rubin GPU clusters via BlueField-4 DPUs and Spectrum-X Ethernet.
DRAMNAND flashAMD, Hewlett Packard Enterprise (HPE) and 3 totalTrendForce
According to Commercial Times, AMD has begun shipping its Venice SP7 processors, which combine TSMC's N2 (2nm) process with CoWoS-L advanced packaging; per The Next Platform, Venice uses TSMC's 6nm process for its I/O dies alongside 2nm compute chiplets. The enterprise-focused SP8 platform is expected to follow in the first half of 2027, and Verano and Venice-X are scheduled to ship in the second half of 2027. The subsequent Verano platform is reportedly set to adopt the N2P node; citing supply chain sources, the report adds that AMD plans to adopt TSMC's A14 process for its Zen 7 architecture, expected to debut in 2028. On packaging, per Commercial Times, ASE and SPIL are participating in the development and validation of wafer-level 2.5D bridge interconnect technology, while AMD has completed validation of panel-level embedded fan-out bridge (EFB) interconnect technology with PTI. On specifications, Venice offers configurations with up to 256 cores and 512 threads, plus high-frequency models reaching 5.3GHz; per Economic Daily News, AMD states the SP7 platform delivers up to twice the performance of its predecessor Turin and 40% better performance per watt in general-purpose workloads. Additionally, in its November 10 announcement, AMD introduced Helion rack configurations designed for agentic AI workloads, with some high-density systems supporting up to 73,728 threads per rack; per Economic Daily News, Foxconn, Compal, Inventec, and Wiwynn are among the partners, the ecosystem includes more than 10 certified configurations, and initial shipments are expected to begin in November. Per Commercial Times and Economic Daily News, AMD expects the addressable data center CPU market to grow from US$26 billion in 2025 to US$220 billion by 2030, a compound annual growth rate of over 50%.
server CPU2nm compute chiplets6nm I/O diesAMD, TSMC and 9 totalTrendForce
AMD announced the AMD EPYC Embedded 9006 Series SP7 CPUs, expanding its x86 processor portfolio optimized for embedded customer requirements and deployments. Built on the 'Zen 6' core architecture, the CPUs combine up to 256 cores, scalable PCIe Gen 6 and CXL 3.1 connectivity, and security from secure boot through runtime. They offer a throughput increase of up to 1.8x compared with the previous generation 5th Gen AMD EPYC 9005 Series processors, targeting semiconductor automated test equipment (ATE), enterprise storage and network firewall applications. The series also provides seven-year product longevity, support for post-quantum cryptography for firmware signing, and ongoing security updates. This is a product launch announcement with no price change, capacity change or discontinuation information; the source does not state the cause (no causal event).
AMD EPYC Embedded 9006 Series SP7 CPUsAMDTechPowerUp
Reported on 2026-11-11: Amid reports that TSMC is exploring 3D DRAM production at NVIDIA's urging, Charles Kau, dubbed the “Godfather of DRAM” and former president of Taiwan's Nanya Technology, dismissed the possibility, arguing TSMC would never venture into DRAM manufacturing; according to Tom's Hardware citing a company spokesperson, TSMC has pushed back against the speculation, reaffirming its commitment to its core foundry business. Kau flagged a greater threat in China's CXMT's aggressive expansion: according to TechNews citing Kau, CXMT is building 10 wafer fabs across Beijing, Shanghai and other locations, with massive new capacity expected to come online within two years, and he warned the expansion could trigger a global memory supply glut and squeeze Taiwanese suppliers, even if CXMT remains reliant on mature processes due to EUV restrictions. CXMT is also targeting the launch of 4F²-based DDR5 RDIMMs by year-end, but Kau questioned whether the architecture could reach mass production, arguing that even substantial R&D spending may not overcome its technical barriers. According to TechNews citing Kau, DRAM scaling remains at 6F², with no manufacturer yet achieving 4F²; DRAM's one-transistor, one-capacitor structure makes further miniaturization particularly challenging, with capacitor scaling and leakage posing major obstacles, and these constraints also complicate 3D DRAM development; he stressed that even industry heavyweights Samsung and Micron have yet to overcome these hurdles, casting further doubt on CXMT's ambitious timeline. Separately, Kau noted the competitive landscape differs in NAND flash: China's YMTC, whose early development he personally led, has emerged as a global technology leader, even licensing patents to Samsung and Micron; unlike China's logic foundry sector, which remains constrained by limited access to EUV lithography equipment, its flash memory industry holds a competitive edge backed by substantial fundraising capabilities. Kau also cited industry precedent: TSMC affiliate Vanguard International Semiconductor (VIS), whose unsuccessful venture into memory manufacturing led it to refocus on foundry operations, underscoring the challenges of crossing between the two businesses.
At a press event in Las Vegas last week, AMD disclosed architectural details of its Zen 6 core. The core promises an average 27 percent uplift in instructions per clock (IPC) across a variety of AI and server workloads, with boosted clocks of 4.1 to 5.3 GHz, and Epyc chips boasting up to 256 cores — though not all on the same SKU. Zen 6 comes in two flavors: a frequency-optimized variant (Zen 6) and a density-optimized version (Zen 6c); both share the same ISA with clock speed as the main differentiator, with Zen 6c given deeper scheduler queues for higher-latency workloads while Zen 6's shallower queue enables higher clocks on less power. AMD claims a 20 to 31 percent IPC uplift over Zen 5 for cloud and AI workloads, suggesting a 4.1 GHz Zen 6c-based Venice Epyc should deliver performance on par with a 5 GHz Zen 5-based Turin Epyc. Cache per core is now a constant 4 MB; Zen 6 natively supports FP16 datatypes and doubled the VNNI-INT8 pipes from two to four. The article notes client-side gains may differ, citing the roughly 5 percent gaming gains reported for Ryzen 9000-series, and AMD fellow Mike Clark says PC buyers expect more than a 6 percent gain from Zen 6. The cores will eventually power AMD's next generation of Ryzen processors, but AMD is not yet ready to discuss Ryzen, and the products have not launched.
AMD has confirmed that its cache-packed Epyc X-series chips are officially making a comeback after a three-year hiatus. The HPC-optimized Venice-X parts will offer up to 96 cores and use AMD's 3D V-Cache chip-stacking technology to triple L3 cache density to more than a gigabyte. First teased at CES earlier this year, the chips are primarily aimed at latency-sensitive technical and scientific computing workloads such as computational fluid dynamics and electronic design automation (EDA); AMD expects Venice-X to begin trickling out in the second half of 2027, meaning the parts have not yet shipped. According to AMD Fellow Phil Steinke, keeping more of the model in cache means CPU cores do not have to wait as long for data to move in and out of system memory. Prior history: the stacking tech debuted in the Ryzen 7 5800X3D in 2022, reached the Milan Epyc generation later that year, and a second generation of X-series Epycs launched in 2023, but when AMD unveiled its 5th-gen Epycs in late 2024 there was no Turin-X on the roadmap. Madhu Rangarajan, who runs AMD's compute and enterprise AI products business, said this was intentional: the enterprise HPC market has a slower cadence, so AMD does not do an X chip every generation. In Venice-X, each of up to eight CPU dies is bonded to a 96 MB SRAM tile, for 144 MB of L3 per chiplet or 1,152 MB per socket — the same as the Genoa-X parts they replace; core count and cache capacity are unchanged, but clock speeds rise from Genoa-X's 3.7 GHz to 5.3 GHz because the SRAM tile was moved from the top to the bottom of the stack in the Zen 5 generation, easing the trapped-heat limitation, so customers no longer have to choose between big caches and high clocks.
Epyc Venice-X (HPC-optimized Epyc X-chip with 3D V-Cache)AMDThe Register
AMD's unreleased Verano processors (planned status) are designed specifically to power AMD's next generation of GPU servers; Madhu Rangarajan, CVP of AMD's compute and enterprise AI products business, described them at a press event in Las Vegas as the first step toward something resembling Nvidia's Vera Rubin superchips: 'Verano is really designed for an integrated CPU+GPU rack scale solution,' with a Verano+GPU solution competing against Vera+Rubin. The chip features six CCDs for a total of 72 high-frequency cores clocking to 5.3 GHz, or 192 density-optimized cores clocking to 4.1 GHz; it has an entirely custom pair of I/O dies with four LPDDR5X memory controllers, currently being validated for 24 channels of memory at up to 8,533 MT/s. Peak theoretical memory bandwidth tops out at around 800 GB/s — about half of AMD's top-specced Venice parts and about 66 percent of Nvidia's Vera — while LPDDR buys a 30 to 40 percent reduction in power consumption compared to RDIMMs. In its first incarnation Verano won't be socketed, using a soldered BGA, and its memory uses the same SOCAMM2 modules as Nvidia's Vera-Rubin. Verano's xGMI links top out at 112 Gbps per lane versus Venice's 64 Gbps (PCIe 6.0 level), near PCIe 7.0 bandwidth. The article says the part starts shipping next year (no absolute date given), with more info expected closer to the MI500X's debut next year; AMD has not disclosed the CPU-to-GPU ratio for Verano, and the GPUs are assumed to be MI500X. AMD does not expect Verano to replace Venice in every AI rack; its Helios rackscale systems will feature 18 96-core Venice CPUs paired to 72 Instinct MI455X GPUs.
Verano处理器Venice Epyc处理器Nvidia Vera Rubin超级芯片AMD, NvidiaThe Register
This is a paid press release. Contact the press release distributor directly with any inquiries. TI redefines embedded development with agentic AI in its CCStudio™ ecosystem, empowering engineers to accelerate innovation PR Newswire Tue, November 10, 2026 at 9:00 AM GMT+1 5 min read TXN Agentic AI integration at every stage of embedded development dramatically shortens time to market, including a purpose-built skill that reduces software migration time from months to days News highlights: TI is strengthening the agentic capabilities of its CCStudio ecosystem, pairing industry-standard AI agents and models with its expansive resource library to deliver highly accurate results when developing with TI MCUs, as well as wireless connectivity and radar devices. The industry's first agentic device migration skill reduces software migration timelines from months to days, giving engineers the flexibility to seamlessly transition between compatible MCUs without sacrificing existing software investments. The CCStudio development ecosystem works across developers' environments, including Visual Studio Code, bringing TI-specific context, tooling and device knowledge into different AI…
US materials company Advanced Chip and Circuit Materials (ACCM) is expanding its manufacturing capacity in La Crosse, Wisconsin, for its Celeritas family of dielectric materials for AI hardware. According to an ACCM press release, its prepreg and build-up capacity will reach 87 million square feet (about 8.1 million square metres) a year this month, and new laminate capacity of 20 million square feet (about 1.9 million square metres) a year comes online in January 2027; larger expansions of both are planned for the second half of 2027. The source does not state the cause of the expansion. The materials none of which depends on T-glass or quartz fabric, which are in short supply, are made on a raw material supply chain independent of the conventional CCL chain, with lead times of typically three weeks, per ACCM. The expansion covers four segments: ultra-low-loss materials without woven glass for 224G-class switch and backplane designs, low and negative expansion laminates for large accelerator boards, core materials for IC substrates and packages, and build-up materials. ACCM says the materials are halogen-free and PFAS-free, and can be processed on the lamination, drilling and plating equipment PCB makers already use. The company is also opening a second materials characterisation laboratory at the Wisconsin facility and has not disclosed the size of the investment or how its capacity compares with demand.
Celeritas family of dielectric materials for AI hardwareultra-low-loss materials without woven glasslow and negative expansion laminatesAdvanced Chip and Circuit Materials (ACCM)EvertiqCapacity Change
Y-S Electronic, a subsidiary of Sun Yad Group, reported consolidated revenue of NT$73.271 million (US$2.24 million) in October 2026, up 31.67% year-on-year. Revenue for the first 10 months reached NT$792.871 million, up 23.20% year-on-year, surpassing its full-year 2025 revenue of NT$782.351 million, highlighting continued momentum in its core businesses. The source does not state the cause.
South Korean smartphone camera module maker Namuga has signed a memorandum of understanding (MOU) with US FPGA company Altera to jointly develop robotic sensor systems. The MOU, covering robotics and physical artificial intelligence (AI), was signed on Nov. 6 at the 2026 Namuga Tech Day held at Namuga's headquarters in Pangyo, Seongnam. The companies will combine Namuga's three-dimensional (3D) sensing technology with Altera's FPGAs to jointly develop multisensor devices for robots, collaborating on hardware and software design through manufacturing using Nvidia's platform. A key development target is a sensor system based on Nvidia Holoscan Sensor Bridge (HSB), which transmits data collected by cameras, LiDAR and other sensors to GPUs over Ethernet, with FPGAs collecting and preprocessing sensor data to reduce transmission latency for real-time AI processing. Altera already offers an FPGA-based HSB solution, and Namuga plans to integrate its proprietary 3D sensing technology into it. The partnership aims to expand Namuga's business beyond camera module supply into sensor data processing systems and reduce its heavy reliance on smartphone-related revenue: mobile products once accounted for 99% of total revenue, a share that has recently declined to 96%, and Namuga aims to raise the non-mobile contribution to more than 10% by 2028, when it expects related revenue to begin materializing in earnest. Namuga CEO Lee Dong-ho identified four new growth areas: Vision Expansion (VX), mobility, security and healthcare.
robotic sensor systemscamera modulesFPGANamuga, Altera and 6 totalThe ElecPartnership/M&A
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Namuga, Altera, Samsung Electronics, Nvidia, Intel, Silver Lake
Key Takeaways Verizon yields 6.1% at its current dividend, against 2.0% for Texas Instruments, which raised its dividend 7% in September. Texas Instruments grew its dividend 8.1% a year from fiscal 2020 to fiscal 2025, against 1.9% a year for Verizon. Verizon’s dividend took 52% of its free cash flow over the twelve months to Sept. 30, 2026, against 71% at Texas Instruments, whose dividend outran its free cash flow from fiscal 2023 to fiscal 2025. SpaceX’s push into mobile service is the main risk to watch for Verizon. Verizon Communications ( VZ ) had a rough October. Its stock fell 9% on Oct. 9, its worst day since 2002, after SpaceX agreed to buy a nationwide block of low-band spectrum for its Starlink Mobile service. Texas Instruments ( TXN ) is having a much better fall. It raised its quarterly dividend 7% to $1.52 a share on Sept. 17, marking what it calls “23 consecutive years of dividend increases,” and reported third-quarter revenue up 28% on Oct. 21. So income investors have a choice: Verizon’s 6.1% yield, or Texas Instruments’ faster-growing dividend. With $10,000 to invest, which pays you more over the next 10 years? Metric Verizon (VZ) Texas Instruments (TXN) Dividend…
Renesas Electronics Corporation (TSE:6723) introduced the RZ/T2N, a 64-bit microprocessor (MPU) that combines high-precision real-time motor control, industrial Ethernet and application processing on a single chip. The device has dual Arm Cortex-A55 cores (up to 1.2 GHz) for application processing and two Cortex-R52 cores (up to 800 MHz) for real-time processing; each Cortex-R52 core has 576 KB of tightly coupled memory (TCM) with ECC, and the chip integrates motor control peripherals for up to four axes, enabling single-chip motor control for industrial robots such as SCARA and delta robots. Encoder interfaces provide two channels per axis and support Tamagawa T-Format, HIPERFACE DSL, A-format, EnDat 2.2 and BiSS C, as well as the latest EnDat 3 and BiSS Line protocols. The chip includes three Gigabit Ethernet MACs (GMACs), an Ethernet switch and an EtherCAT SubDevice Controller (ESC), supports major industrial Ethernet protocols including EtherCAT, PROFINET RT/IRT and EtherNet/IP, redundancy protocols including HSR, PRP and FRER, and security features including a cryptographic library, secure boot, secure firmware update and Arm TrustZone; it supports 16-bit LPDDR4-1600 memory with on-the-fly decryption/encryption, ECC protection across all memory, and shares a common Linux package and Flexible Software Package (FSP) with the RZ/T2x and RZ/N2x series. Functional safety software solutions, proven on the RZ/T2x and RZ/N2x series, are planned for availability in the second half of 2027. The product will be demonstrated live at electronica 2026, November 10–13 in Munich, Germany (Renesas booth: Hall C5, Stand 479).
According to a report by the Southern China Morning Post published 9 November 2026, Huawei has introduced its first desktop PCs powered by its own 10-core processor and proprietary HarmonyOS operating system, the Qinyun HM650 and HM650g. The machines come with 16 GB of LPDDR5 memory (probably made by China's CXMT) and either a 256GB or 512GB SSD (probably made by Chinese flash maker YMTC), and are powered by Huawei's Kirin X90 system-on-chip, which originally debuted in Huawei's consumer systems in 2025. The Kirin X90 features 10 Huawei-designed Armv8-based Taishan CPU cores in a 4+4+2 configuration, with all cores supporting simultaneous multithreading (SMT) to execute up to 20 threads simultaneously; the chip also integrates Huawei's Maleoon graphics processing unit (Arm Mali-based) and a dedicated neural processing unit for AI workloads. Huawei does not officially disclose the Kirin X90's manufacturing process, but a teardown analysis by TechInsights confirmed the CPU is manufactured by SMIC using its 7nm-class N+2 process technology, which trails leading-edge nodes from Intel, TSMC, and Samsung. Huawei claims all of the new system's components, including the processor, memory, storage, power supply, and wireless connectivity, are manufactured domestically; however, the article notes these chips are still made using foreign manufacturing equipment (from the Netherlands, U.S., and Japan), materials (from Japan), intellectual property (from the UK), and EDA software (from the U.S. and partly from China). The machines run HarmonyOS Enterprise Edition, which uses Huawei's own kernel and software architecture (unlike earlier HarmonyOS versions that incorporated Linux components), but compatibility with existing Windows applications could remain a limitation for enterprise customers that rely on software by multinational corporations for Windows. The source does not state any market-level cause; it cites national security and domestic supply chains inside the sanctioned country as the context for Huawei's 'entirely domestic' claim.
Kirin X90 system-on-chipHarmonyOS Enterprise EditionLPDDR5 memoryHuawei, SMIC and 5 totalTom's Hardware
South Korea's LX Semicon has begun mass production of the LX61101, an automotive motor control MCU, for Hyundai Motor and Kia. LX Semicon said this marks its first achievement in automotive MCUs, a new business it has been developing, and the first domestically produced MCU to be used in Hyundai Motor and Kia vehicles. The LX61101 is an MCU optimized for motor control in automotive body electronics; it enables real-time motor control by monitoring speed, position, rotational direction, and torque, and is characterized by an ultra-compact design, high performance, and high system efficiency. Beginning with vehicles that Hyundai Motor and Kia plan to produce in the second half of this year, the LX61101 will be applied to a broader range of vehicle models. LX Semicon was selected as a new business partner for a motor-specialized MCU through Hyundai Motor and Kia's supplier selection process in March 2023 and received a supplier award in April of the same year. The LX61101 was developed and mass-produced with the support of domestic companies across the full supply chain management (SCM) process, including semiconductor design, foundry manufacturing, and back-end processing.
According to DIGITIMES Intelligence, global server shipments are forecast to reach 4.89 million units in the fourth quarter of 2026, up 5.5% sequentially, marking the year's strongest quarterly growth despite mounting concerns over the AI market. Arm-based CPU servers are expected to lead the expansion, while Nvidia's next-generation Vera Rubin platform faces supply constraints. These figures are forecasts, not achieved results; the source does not state the cause of the Vera Rubin supply constraints.
Arm-based CPU serversNvidia Vera Rubin platformNvidiaDigiTimes Asia
According to EE Times Asia, AI-driven CPU and memory demand is tightening supply of high-capacitance MLCCs, with shortages forecast through mid-2027 (first half of 2027). The source does not state additional specific causes, affected manufacturers, or part numbers; the shortage is a forecast with a stated horizon through mid-2027, and no quantified actual shortage data is reported.
Recent earnings reports from Apple and Intel highlight growing supply-chain strain, which the source attributes to soaring memory costs and massive AI infrastructure build-outs. DIGITIMES analyst Luke Lin identified two supply-chain signals: first, Apple is locking in capacity through aggressive long-term procurement; second, Intel is taking the unusual step of converting 18A capacity back to the older Intel 3 node to chase urgent server CPU demand. The source does not specify the implementation status or completion timing of this capacity conversion.
Duksan Hi-Metal disclosed on Nov. 5 that third-quarter revenue reached 99.5 billion won and operating profit totaled 10.2 billion won, up 61.9% and 552.9%, respectively, from a year earlier, breaking its quarterly records for both revenue and operating profit for the second consecutive quarter; quarter-over-quarter, revenue increased 9.7% and operating profit rose 1.5%. Cumulative nine-month revenue reached 259 billion won and operating profit 19.6 billion won, up 9.6% and 600%, respectively, from the corresponding full-year figures for 2025. The company attributed its improved performance to its flagship solder ball products, and core solder balls also recorded growth; the company said it expects to continue pursuing profitability-focused growth in 2027 by expanding high-value-added products, including micro solder balls measuring less than 130 micrometers in diameter (a company expectation/plan, not an achieved result).