[News] AMD EPYC Venice CPUs Begin Shipping on TSMC 2nm; Verano Reportedly to Adopt N2P, with A14 Planned for 2028
What happened
According to Commercial Times, AMD has begun shipping its Venice SP7 processors, which combine TSMC's N2 (2nm) process with CoWoS-L advanced packaging; per The Next Platform, Venice uses TSMC's 6nm process for its I/O dies alongside 2nm compute chiplets. The enterprise-focused SP8 platform is expected to follow in the first half of 2027, and Verano and Venice-X are scheduled to ship in the second half of 2027. The subsequent Verano platform is reportedly set to adopt the N2P node; citing supply chain sources, the report adds that AMD plans to adopt TSMC's A14 process for its Zen 7 architecture, expected to debut in 2028. On packaging, per Commercial Times, ASE and SPIL are participating in the development and validation of wafer-level 2.5D bridge interconnect technology, while AMD has completed validation of panel-level embedded fan-out bridge (EFB) interconnect technology with PTI. On specifications, Venice offers configurations with up to 256 cores and 512 threads, plus high-frequency models reaching 5.3GHz; per Economic Daily News, AMD states the SP7 platform delivers up to twice the performance of its predecessor Turin and 40% better performance per watt in general-purpose workloads. Additionally, in its November 10 announcement, AMD introduced Helion rack configurations designed for agentic AI workloads, with some high-density systems supporting up to 73,728 threads per rack; per Economic Daily News, Foxconn, Compal, Inventec, and Wiwynn are among the partners, the ecosystem includes more than 10 certified configurations, and initial shipments are expected to begin in November. Per Commercial Times and Economic Daily News, AMD expects the addressable data center CPU market to grow from US$26 billion in 2025 to US$220 billion by 2030, a compound annual growth rate of over 50%.
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Affected components and suppliers
Source and time
Source: TrendForce · 11/10/2026 · View original source
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