AMD's Epyc X-chips are back after a three-year hiatus

What happened

AMD has confirmed that its cache-packed Epyc X-series chips are officially making a comeback after a three-year hiatus. The HPC-optimized Venice-X parts will offer up to 96 cores and use AMD's 3D V-Cache chip-stacking technology to triple L3 cache density to more than a gigabyte. First teased at CES earlier this year, the chips are primarily aimed at latency-sensitive technical and scientific computing workloads such as computational fluid dynamics and electronic design automation (EDA); AMD expects Venice-X to begin trickling out in the second half of 2027, meaning the parts have not yet shipped. According to AMD Fellow Phil Steinke, keeping more of the model in cache means CPU cores do not have to wait as long for data to move in and out of system memory. Prior history: the stacking tech debuted in the Ryzen 7 5800X3D in 2022, reached the Milan Epyc generation later that year, and a second generation of X-series Epycs launched in 2023, but when AMD unveiled its 5th-gen Epycs in late 2024 there was no Turin-X on the roadmap. Madhu Rangarajan, who runs AMD's compute and enterprise AI products business, said this was intentional: the enterprise HPC market has a slower cadence, so AMD does not do an X chip every generation. In Venice-X, each of up to eight CPU dies is bonded to a 96 MB SRAM tile, for 144 MB of L3 per chiplet or 1,152 MB per socket — the same as the Genoa-X parts they replace; core count and cache capacity are unchanged, but clock speeds rise from Genoa-X's 3.7 GHz to 5.3 GHz because the SRAM tile was moved from the top to the bottom of the stack in the Zen 5 generation, easing the trapped-heat limitation, so customers no longer have to choose between big caches and high clocks.

Impact and signal

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Source and time

Source: The Register · 11/10/2026 · View original source