Semiconductor reliability testing company QRT disclosed on Nov. 13 that consolidated revenue for the January-September period of 2026 reached 57.814 billion won, up 11.7% from a year earlier, while operating profit totaled 5.871 billion won, up 54.9%. Operating margin climbed 2.8 percentage points to 10.1% from 7.3%. Revenue from its core reliability testing business rose 17.1% year-on-year to 34.861 billion won, with its share of total revenue increasing to 60% from 58%; equipment sales, a new business segment, reached 1.666 billion won, about 3% of total revenue. The company attributed the growth to rising demand for space component reliability testing and next-generation glass substrate evaluation. QRT expects stable performance to continue in the fourth quarter, with revenue from radio-frequency (RF) reliability testing equipment ordered by a European defense company earlier this year expected to be reflected in results. The company plans to launch a new business targeting servers for AI data centers and to expand its reliability testing services in the U.S.
Cerebras Systems reported third-quarter 2026 results, delivering record core revenue of US$231 million, up 10% sequentially and 70% year-over-year, and positive core net income of US$30 million, its first positive non-GAAP net income as a public company.
On Nov. 12, DB HiTek disclosed its preliminary consolidated third-quarter results: revenue of 403.36 billion won, up 14% from a year earlier, and operating profit of 90.02 billion won, up 6.58% year-on-year. For the first nine months, cumulative revenue reached 1.1774 trillion won and operating profit 262.2 billion won, increases of 19% and 24% respectively from a year earlier. The improvement was driven by its power semiconductor foundry business, with strong performance in the 8-inch foundry business; foundry utilization remained effectively at 100% in the third quarter, and average selling prices also increased as the share of higher-value high-voltage BCD (HV BCD) power semiconductors expanded. The company is strengthening its foundry competitiveness through high-value products including HV BCD, third-generation superjunction MOSFETs (SJ MOSFETs) and specialty CMOS image sensors (Specialty CIS). It recently completed a cleanroom at its Sangwoo Campus (Fab 2) in Eumseong County, North Chungcheong Province, and plans to add monthly production capacity of 40,000 wafers through medium- to long-term investments, with Fab 2's next-generation power semiconductor capacity set to rise from the current 63,000 wafers per month to more than 100,000 (this expansion is planned). Net profit totaled 22.48 billion won, down 75.23% from a year earlier and 80.56% from the previous quarter; the decline appears to reflect losses stemming from the temporary suspension of ferroalloy operations at subsidiary DB World in May, as well as non-operating losses related to foreign exchange and investments.
power semiconductors8-inch foundry wafershigh-voltage BCD (HV BCD) power semiconductorsDB HiTek, DB WorldThe ElecFinancial/Earnings
ISC said on Nov. 12 that it held a groundbreaking ceremony for its new fab in the Songdo Knowledge and Information Industrial Complex in Incheon, planning to invest about 35 billion won to consolidate its domestic production facilities (currently in Seongnam and Ansan) and core R&D operations at the single Songdo site, with construction scheduled for completion by 2027 and full operations set to begin in 2028. The project is part of a 100 billion won medium- to long-term investment plan announced in September, under which ISC will allocate 35 billion won each to its Songdo and Vietnam production sites, with the remaining 30 billion won used to introduce manufacturing AI and upgrade production and quality management systems at the two locations. The new fab will handle customized design of high-performance test sockets and initial mass production of new products, while Vietnam factories will handle mass production for global customers. ISC plans to expand its annual test socket production capacity in South Korea and overseas from 2 million units this year to 3 million in 2027, 4 million in 2028 and as many as 5 million in 2029. The expanded production line at its first Vietnam factory began full operations in October, and the second Vietnam factory is scheduled to begin mass production in the second quarter of next year.
Panmnesia said on Nov. 12 that it signed a memorandum of understanding (MOU) with Intel Korea to cooperate on Compute Express Link (CXL) technology. The signing ceremony took place at COEX in Seoul during the Intel AI Summit Seoul 2026 event. The companies plan to integrate Panmnesia's interconnect semiconductor chips, including CXL switches, with Intel's Xeon server CPU platform, with the goal of supplying CXL-based servers to operational AI data centers. They will also explore device interoperability testing and performance optimization for AI workloads, and plan to gradually develop reference architectures for rack-scale AI computing infrastructure and conduct proof-of-concept (PoC) testing. Panmnesia's PCIe 6.4-CXL 3.2 Fusion Switch supports both PCIe and CXL on a single chip, extending CPU memory expansion and sharing capabilities to the rack level through switch-to-switch cascading and connections between switches and other devices; Panmnesia has secured physical chips of this switch, and performance has been optimized through the integration of its low-latency CXL 3.2 controller. Panmnesia also joined the Intel-led K-AI Full Stack Alliance, which aims to develop domestically designed servers incorporating Intel CPUs and participating companies' switches, memory and accelerators, and plans to facilitate the adoption of CXL environments.
Siemens has signed an agreement to acquire Lauterbach, a German provider of debug and trace solutions for embedded software and complex system-on-chip (SoC) architectures. Lauterbach develops modular development and verification tools for microprocessors and embedded CPU cores, including hardware-assisted debuggers and real-time trace tools. Siemens said the combination of complementary technologies enables a unified view of chip and software behavior and helps customers more quickly identify errors arising from complex hardware-software interactions during chip development, extending its EDA portfolio for semiconductor design. The transaction is expected to close in the first half of 2027, subject to customary closing conditions and required regulatory approvals, and has not yet been completed.
microprocessorsembedded CPU coresASICSiemens, LauterbachEvertiqPartnership/M&A
CMC Magnetics reported consolidated revenue of NT$6.17 billion (US$187.29 million) for the first three quarters of 2026, up 17% year on year, which the source attributes to growth in its core businesses and its Storage & Power (S'n'P) strategy beginning to show results. Operating profit reached NT$311 million, nearly 20 times its level a year earlier. Net income totaled NT$2.327 billion, with earnings per share of NT$2.17.
According to a November 12 post on X by leaker Gotou_3rd, AMD's rumored "Siren Halo" APU is claimed to use dedicated GDDR7 VRAM (written as "dedicated GD7 VRAM" in the post) while LPDDR system memory would still be present, i.e., two separate memory pools; AMD has not confirmed this, and it remains a rumor. The leaker claimed Siren Halo follows Medusa Halo, that Siren Point is basically a Medusa refresh, and that the new name exists because AMD won't have a fully new Halo design in 2027; no capacities, bus widths, or launch timing were given. Background: AMD added GDDR7 support to its Linux driver in September, a change widely tied to RDNA 5; the existing Strix Halo and its Gorgon Halo refresh use a single LPDDR5X pool shared by the CPU and GPU, with the Ryzen AI Max+ PRO 495 supporting up to 192 GB, of which up to 160 GB can go to graphics, a key reason these chips are popular for local LLM inference. The leaker also suggested Siren Halo could be related to Magnus, the AMD chip linked to Microsoft's Project Helix, though that is speculation; AMD hasn't confirmed Siren Halo at all.
According to a November 13, 2026 report, TSMC pushed back against 3D DRAM manufacturing rumors, reaffirming its commitment to its core foundry business, and industry sources indicate that despite having no concrete plans to manufacture DRAM itself, TSMC is involved in embedded DRAM, HBM base dies and wafer-to-wafer stacking for Qualcomm. Embedded DRAM: in 2007 TSMC said it had produced its first 65nm eDRAM customer products; in March 2008 it said its 40nm 40G and 40LP processes could be paired with embedded DRAM; per an eeNews Europe report back in 2025, its 22nm MRAM is in production, with 16nm ready for customers and 12nm in development. HBM base dies: per TrendForce, HBM base dies are expected to increasingly adopt TSMC's advanced nodes starting with HBM4E, with some suppliers possibly turning to TSMC's 12nm process for standard HBM products and customized designs potentially pushing into 3nm; SK hynix and Micron are reportedly poised to tap TSMC for custom HBM4E base die production; per The Elec, Micron president and CTPO Scott J. DeBoer revealed at the company's September 30 earnings event that both its NVIDIA co-designed NVHBM and JEDEC-standard HBM4E are being developed using foundry-manufactured base dies, a departure from Micron's HBM4 approach that relied on an internally developed base die; per Seoul Economic Daily, NVIDIA has asked Samsung, SK hynix and Micron to use TSMC's 3nm process for the base dies of its NVHBM, unveiled in August, aiming to standardize manufacturing across suppliers, ensure consistent performance and streamline product validation. Qualcomm HBC: Qualcomm validated its first chips featuring HBC technology in early November, HBC is expected to debut in the Dragonfly AI250 accelerator with sampling slated for 1H27 (per ServeTheHome), placing LPDDR memory directly atop the compute die; per an August report by The Elec, Samsung and SK hynix are working with Qualcomm on commercialization and are expected to handle DRAM stacking, while TSMC is reportedly poised to contribute technology integration and advanced packaging expertise. Multiple items described here are reported plans or rumors, not achieved results. The source does not state the cause beyond the reported rationale of standardizing manufacturing.
3D DRAMembedded DRAM (eDRAM)HBM base dieTSMC, Qualcomm and 6 totalTrendForce
AP Systems said on Nov. 10 that new orders for its semiconductor business had exceeded 100 billion won as of November, about 1.5 times the division's revenue of 65.2 billion won last year, with revenue from the orders to be recognized through 2027. The growth was driven by increased orders for rapid thermal processing (RTP) equipment, one of the company's core technologies; AP Systems entered the semiconductor RTP market with its KORONA RTP 800, jointly developed with Samsung Electronics beginning in 1999, and the equipment is supplied for NAND flash and DRAM manufacturing processes. The company said it has expanded its market share among South Korean memory chipmakers as RTP equipment is increasingly adopted in front-end manufacturing, and has broadened its portfolio to include RTP systems for next-generation DRAM and automation equipment, adding that if customers continue expanding capacity there is significant potential for additional deliveries to similar processes within the same fab. AP Systems has also begun supplying laser-based semiconductor equipment and aims to raise the semiconductor business's share of total revenue to 30% by 2030, up from less than 20% currently. The company separately said on Nov. 6 that consolidated third-quarter revenue totaled 488.2 billion won with operating profit of 31.6 billion won, most of it from OLED-related businesses.
Silicon Valley startup KORA Systems is developing an AI-centric operating system, KORA OS, in partnership with Qualcomm. The OS was officially announced on Nov. 10 (local time) and is scheduled for release in the second half of 2027 (a plan, not yet released). The company co-designed the OS with Qualcomm over the past year, optimizing it for the Snapdragon X2 Elite platform's SoC architecture, and it also supports Intel and AMD processors. CEO Curt McMaster said that once KORA OS becomes established, the company plans to introduce a mobile version running on high-performance Qualcomm mobile chips, with no specific date given. KORA Systems was formerly Playtron, a gaming OS developer, and changed its name in July 2025 after shifting focus to AI-centric OS development; KORA incorporates technology from GameOS, a Linux-based OS developed during the Playtron era. The partnership began at Qualcomm's Snapdragon Summit last year: after HUMAIN CEO Tareq Amin unveiled plans for an enterprise AI OS based on Snapdragon X2 Elite, McMaster reached out first, leading to joint development of HUMAIN OS and evolving into collaboration with Qualcomm. KORA and HUMAIN OS share the same technology architecture (Linux desktop environment, AI agent platform, Cortex hybrid inference engine and Neural Workspace) but target different users: HUMAIN OS is for enterprises while KORA targets developers and creators who actively use AI agents. KORA Systems said the Snapdragon X2 Elite can simultaneously run a 26-billion-parameter LLM, along with speech recognition and conversion models, entirely on-device.
KORA OSHUMAIN OSKORA Systems, QualcommThe ElecPartnership/M&A
AMD officially launched its sixth-generation EPYC server CPUs (codenamed Venice) based on the Zen 6 microarchitecture on Nov. 10. The processors are now commercially available, with major server manufacturers beginning shipments of Venice-based systems, and hyperscale cloud providers including Microsoft Azure and Oracle Cloud Infrastructure (OCI) planning to make VM instances powered by the processors available to general customers soon. AMD divided the Venice lineup into three categories: GPU host nodes, multi-agent AI workloads, and general-purpose enterprise computing. In the GPU host-node category, a high-frequency 96-core model delivers 1.8 to 1.9 times the AI inference output throughput on Nvidia B200 GPUs versus fifth-generation EPYC processors. The EPYC 9996 scored 5,470 points in the SPECrate 2017 integer benchmark versus 1,459 points for a system powered by Nvidia's Vera CPU (both dual-socket), a performance advantage of up to 3.75 times; versus Intel's sixth-generation Xeon Granite Rapids 6980P it delivered 2.74 times higher performance by geometric mean of multiple benchmarks, including 3.45 times higher planning and orchestration performance in TPCx-AI, 2.83 times higher web gateway request throughput measured with WRK and NGINX, 2.65 times higher performance across enterprise tools and network workloads, and 2.5 times higher ephemeral tool execution performance. The EPYC 9996 features 256 cores, a 600-watt default CPU power (DCP) rating and is priced at $14,904, versus Intel's Xeon 6980P with 128 cores, a 500-watt TDP and a $13,955 price. AMD also announced the sixth-generation EPYC Embedded 9006 Series SP7 CPUs for the embedded computing market. The source states the launch aims to expand market share by offering better price-performance efficiency than competing products.
server CPUEPYC 9996EPYC Embedded 9006 Series SP7AMDThe Elec
Samsung Electro-Mechanics plans to focus on mass production of high-value-added MLCCs in the Philippines and Busan starting next year, shifting its MLCC strategy toward AI applications.
On Nov. 11, DEEPX announced it received the Hong Dae-yong Award at the 2026 Patent Technology Awards for its patent titled 'Computing Acceleration Device for Artificial Neural Networks Having a Pipeline Structure' (Patent No. 10-2263598). The patented architecture divides the AI accelerator's computing process into six combinational logic circuit stages connected by temporary storage buffers, improving processing speed and power efficiency by reducing the storage and movement of intermediate data generated during AI computations. In a comparison with a conventional design using the same Xilinx XC2VP70 FPGA, computational performance increased 12-fold and memory consumption fell to approximately one-341st of the previous level. Founded in 2018, DEEPX has filed 606 patent applications to date, of which 186 have been registered; its 600th application relates to DX-Newton, an API layer that lets developers retain an Nvidia Isaac-based robotics development environment while replacing only the AI inference acceleration component with a DEEPX NPU. The source does not state the cause.
AI acceleratorneural processing unit (NPU)DEEPXThe Elec
Semiconductor back-end equipment maker Genesem said in a regulatory filing on Nov. 12 that consolidated third-quarter revenue reached 25.154 billion won with operating profit of 2.567 billion won, swinging to a profit from a loss of 372 million won a year earlier; revenue rose 59.5% year-on-year and the operating profit margin stood at 10.2%. Revenue increased as the company sequentially delivered equipment ordered during the first half of the year, and CEO Han Bok-woo said orders secured in the first half were gradually recognized as revenue. Its order backlog stood at 85.417 billion won at the end of September, approximately 1.5 times last year's annual revenue of 56.757 billion won; based on the orders secured, Genesem aims to increase full-year revenue by more than 40% from a year earlier (a target, not an achieved result). Genesem supplies saw singulation equipment for cutting semiconductor packages, wafer mounters used in HBM production, and package sorting equipment, and has commercialized AI-based vision inspection systems for back-end equipment.
Intel announced the official launch of the K-AI Full Stack Alliance on Nov. 11 at the Intel AI Summit Seoul 2026, held at COEX in Seoul, partnering with 23 South Korean companies to build AI infrastructure tailored to the Korean market across hardware, software and AI services, targeting sovereign AI and physical AI markets and centered on domestically manufactured servers powered by Intel chips. Initial participants include KTNF, Dnotitia, Panmnesia, Upstage, Nota AI, DEEPX, FuriosaAI and Exina. Intel Korea will also sign an MOU with Seoul AI Hub to support domestic AI startups. At the event Intel stated it is mass-producing Clearwater Forest, a Xeon server processor with up to 288 high-density, energy-efficient E-cores; it plans to launch Diamond Rapids, with up to 256 high-performance P-cores, next year; and it unveiled a physical chip of its next-generation data center inference accelerator, the Intel GPU D-Series, delivering up to 26,200 TFLOPS of FP4 performance at 350 watts. Compared with the Nvidia RTX 6000 Pro, Intel demonstrated 30% lower latency on Gemma models, 2.2 times higher AI agent performance, and up to 5.9 times higher financial simulation performance (Intel GPU D270).
domestically manufactured servers powered by Intel chipsIntel Core Ultra Series 3Clearwater Forest Xeon server processorIntel, KTNF and 9 totalThe ElecPartnership/M&A
Related manufacturers
Intel, KTNF, Dnotitia, Panmnesia, Upstage, Nota AI, DEEPX, FuriosaAI, Exina
DIGITIMES observes that as AI accelerators continue to grow in size, substrate dimensions are gradually moving beyond 100x100mm, and warpage issues in organic substrates have become increasingly pronounced, prompting industry players to invest in the development of different core-layer materials. Glass, which offers excellent flatness and an adjustable coefficient of thermal expansion (CTE) that can be brought closer to that of silicon, can help reduce warpage, and has emerged as a closely watched core-layer solution and a key focus of future technology development. The source does not specify manufacturers, timelines, or mass-production status.
glass substrate core layerorganic substrateDigiTimes Asia
DB HiTek reported its third-quarter 2026 results, with continued strength in its core foundry operations: the company said demand for power semiconductors kept utilization at virtually full levels, while a richer mix of high-voltage products supported selling prices, lifting operating profit; however, net income fell steeply, showing that operating momentum did not carry through to the bottom line. The company is now preparing to add capacity, though the ramp will depend on customer demand and investment decisions, so the expansion remains at the planning stage and is not confirmed as implemented.
AP Memory Technology reported record-breaking third-quarter 2026 revenue and net profit, driven by surging demand for its integrated passive device (IPD) silicon capacitors under the S-SiCap product family. Order visibility now extends through the second half of 2027. The company is also pursuing a dual-track strategy with UMC. It projects that, as manufacturing capacity expands, silicon capacitor revenue will experience multi-fold growth and surpass its core IoT RAM revenue in 2027 — a forecast, not an achieved result.
Taiwan's National Science and Technology Council (NSTC), on November 11, 2026, proposed expanding the list of national core key technologies from 42 to 46 items, with four additions covering satellite communications, AI chip substrates, drones, and biotechnology. The draft is still under public consultation and must be reviewed by a committee before the Executive Yuan can promulgate it.