Microchip is expanding its space power portfolio with the POL-05-20S, a radiation-tolerant GaN point-of-load converter that delivers up to 20A of output current. The POL-05-20S-T is available in production quantities.
Bare-die shots revealed via the Moore's Law Is Dead YouTube channel have exposed details of Intel's upcoming "Nova Lake" lineup for mobile devices. The "Nova Lake-HX" features an 8+16+4 core configuration with 8 P-Cores, 16 E-Cores, and 4 LPE-Cores, with total silicon measuring 12x30 mm amounting to 360 mm², divided across six dies on various nodes: the graphics tile is built on the Intel 3-E node, embedding 4 Xe GPU cores and covering roughly 26 mm²; a 21 mm² dummy die provides structural integrity of the package; a large 72 mm² die on the Intel 18A-P node hosts 4 LPE-Cores and serves as a central hub; another 18A-P die of 58 mm² functions as a peripheral control tile; the main compute tile is made at an external foundry on the TSMC N2P node and hosts the 8P+16E CPU core configuration, occupying the largest area of 104 mm²; a passive tile of 85 mm² sits beside it for the structural integrity of the package and the intended operation of the "Nova Lake-HX" chip. The less powerful "Nova Lake-H" variant features a 4+8+4 configuration with 4 P-Cores, 8 E-Cores, and 4 LPE-Cores; its package is significantly smaller at 12x23 mm for a total die area of 276 mm². The die configuration remains the same except for the main compute tile, which hosts a 4P+8E-core configuration on the TSMC N2P node occupying 55 mm²; its adjacent passive die is smaller at only 45 mm², while the peripheral control die, central hub die, and graphics tile are all made on Intel nodes and remain the same as in the "HX" variant.
Newegg is discounting an all-AMD 4K gaming PC from CyberPowerPC: the title states a $260 cut, and the article says the rig is now $2,299; a separate deal box shows the CyberPowerPC GM70929 Gaming PC reduced from $2,549.99 to $2,259.49, saving $290.50 (11%). The build includes an AMD Ryzen 7 9800X3D, AMD Radeon RX 9070 XT, 32GB of DDR5 RAM, and a 2TB Gen 4 NVMe SSD, plus a 1000W power supply, ARGB liquid cooling and a B850 motherboard, with a free copy of Onimusha listed at $69.99 at Newegg. The article notes that RAM and SSD price hikes and shortages continue to bite PC builders and that this PC's price is still higher than a few months ago; it also states the 9800X3D was recently dethroned as the fastest gaming CPU by the 9850X3D, that the RX 9070 XT is currently worth $800 in the market, that the 32GB DDR5 RAM is worth at least $400-$450, and that the 2TB SSD is worth $250. The source does not state the cause of the discount.
SK hynix unveiled its ultra-lightweight H-TPU processor for SSD controllers, using just 4% of a conventional CPU core's area and 2.5% of its power. The architecture is designed to ease storage bottlenecks and may also support future HBF applications. The source does not state any price or supply impact.
Intel said on Oct. 15 local time that it will showcase physical AI technologies designed for real-world industrial applications at Web Summit 2026. The demonstrations will feature various types of robots deployed across industries including manufacturing, smart cities, retail and healthcare, and Intel will also introduce its semiconductor chips and AI inference platforms used in these products. Intel said its Core Ultra Series 3 processors, software and partner ecosystem provide practical support for robotics manufacturers and developers, enabling AI systems to move beyond prototypes and operate in real-world environments with high reliability, fast response times and cost efficiency. Web Summit is a global IT and technology exhibition scheduled for Nov. 9-12 in Lisbon, Portugal. the source does not state the cause.
Taiwan-based microcontroller (MCU) manufacturer Holtek Semiconductor unveiled its 2026 product roadmap on October 15, focusing on four core areas: smart protection, green energy and intelligent control, edge AI computing, and general-purpose applications. The title states that AI server cooling orders are set to lift its 2027 revenue.
At an investor relations event on October 15, Chinese display manufacturer BOE said it had completed the full manufacturing process for glass-core substrates, producing 24-layer samples measuring more than 100 × 100mm. The samples have been delivered to customers and passed multiple reliability tests, with further validation underway; mass production remains ahead and has not yet been achieved.
At its earnings briefing on October 15, 2026, TSMC addressed pricing adjustments, CPUs, and advanced packaging, confirming that demand for CPUs related to agentic AI continues to rise as overall AI demand remains strong.
An explosion occurred at Intel's chip plant in Kiryat Gat, southern Israel, on October 14, killing two workers and leaving a third in serious condition. The site makes chips on Intel's capacity-constrained Intel 7 process. As of the report, Intel has not yet said whether production at the plant has been affected, leaving the CPU supply outlook unclear. The source does not state the cause of the explosion.
SK hynix took part in OCP Global Summit 2026, held from the 12th to the 15th of October 2026 in San Jose, California, where it unveiled a wide range of next-generation memory solutions and presented the direction memory technology should take in the AI era. At the exhibition, SK hynix unveiled its second-generation CMM-DDR5 (256GB, based on CXL 3.2), which per the source more than doubles bandwidth (80GB/s) and improves energy efficiency by about 30% compared with the previous generation, and demonstrated CXL pooled memory in AI agent serving and KV cache-sharing scenarios. The source states the background cause: as the volume of data handled by AI grows explosively, data bottlenecks have emerged as a new challenge. SK hynix also showed its product portfolio spanning HBM4/HBM4E/HBM3, HBF, server DDR5 RDIMMs (256GB/128GB/96GB/64GB) and eSSDs. The article also mentions that in September last year SK hynix signed a business agreement with NAVER Cloud, and that the PS1110 E3.S and PS1101 E3.S eSSDs are currently under sequential development.
According to MacRumors, citing Bloomberg's Mark Gurman on his podcast, Apple is reportedly shifting its focus to the M7 chip lineup, skipping higher-end M6 variants as it prioritizes technologies designed for AI workloads; Apple has introduced the base M6 chip in the Mac mini, with M6-powered iMac and entry-level MacBook Pro models also planned, but the company reportedly intends to skip the M6 Pro, M6 Max, and M6 Ultra, moving directly from their M5 predecessors to the M7 lineup. Gurman noted that high-end touchscreen MacBook Pro models featuring M7 Pro and M7 Max chips are expected by the end of 2027, while an entry-level MacBook Pro powered by the standard M7 is also slated for 2027; the M7 Ultra is reportedly planned for the first half of 2028, making a Mac Studio refresh in 2027 unlikely. Per MacRumors, the upcoming OLED MacBook Pro models are expected to retain the M5 Pro and M5 Max chips used in current models, with no processor upgrade planned until 2027. Separately, according to CNBC, Apple and Meta have announced plans to enable developers to run Meta's Muse Spark Open model locally on Apple's high-end Mac Studio desktops; Meta describes Muse Spark Open as its most capable U.S. open-weight model, featuring 816 billion total parameters, 42 billion active parameters, and a 1 million-token context window, built on a mixture-of-experts architecture and designed to run locally on M5 Ultra-powered Mac Studios using Apple's MLX framework; each M5 Ultra supports up to 512GB of unified memory and 1.2TB/s of memory bandwidth, allowing two connected Mac Studios to accommodate the entire model. According to CNBC, a Mac Studio equipped with the required M5 Ultra chip and 256GB of memory starts at $10,799, while a 512GB configuration is expected later this month. Apple has also begun inviting select media representatives to a product launch experience in Los Angeles on Wednesday, October 28.
This is a technical article on FPGA prototyping; it contains no price, capacity, or supply-demand movement. Citing three Wilson Research Group functional verification studies, whose latest is the 2024 FPGA Functional Verification Trend Report, it states that between 2016 and 2024 'design error' as a root cause of ASIC functional flaws fell from 75% to 60% and 'changes in specification' fell from 59% to 43%, while 'incorrect or incomplete specification' went from 56% to 58% to 59% — essentially flat and slightly worse (each figure is the share of respondents citing that cause; multiple answers were allowed, so the numbers do not sum to 100%). The article argues FPGA prototyping can test 'are we building the right chip?' at the specification stage, and describes S2C's Prodigy platform and PlayerPro toolchain: 100+ Prototype Ready daughter cards and reference designs and 50+ Prototype Ready IP blocks; the Prodigy Logic System S8-100, built on the AMD Versal Premium VP1902, carries roughly 100 million ASIC gates per core module, two modules roughly 200 million, four roughly 400 million, with 2,212 XPIOs at up to 56Gbps. Company facts: S2C has spent more than 20 years on ASIC and SoC verification, has more than 300 employees, serves 700+ customers through seven branches and offices worldwide, and since 2020 has served 12 of the world's top 25 semiconductor companies; S2C estimates total cost of ownership runs 30–50% below the legacy EDA suppliers.
According to ZDNet, SK hynix has unveiled its ultra-lightweight Hynix Transaction Processing Unit (H-TPU) architecture, dedicated to SSD data-plane control and transactions, distributing storage-control tasks across dozens of compact H-TPU clusters. According to Vice President Koo In-jae, who oversees SoC design, H-TPU eliminates complex CPU features such as superscalar and out-of-order execution and adopts a simplified four-stage pipeline, reducing processor area to approximately 4% and power consumption to around 2.5% of a conventional CPU core, activating only required modules. Building on H-TPU, SK hynix plans to introduce hardware automation (HWA), assigning repetitive storage-control tasks such as instruction processing, data address lookups, and temporary buffer copying to dedicated hardware circuits. SK hynix expects the H-TPU-based controller architecture to complement high-bandwidth flash (HBF), an emerging memory technology for AI workloads; AI inference is highly read-intensive with read-to-write ratios reaching approximately 300,000 to 1, and AI compilers and runtimes could inform the HBF SoC of upcoming data-processing needs for prefetching. Separately, according to Yonhap News, Samsung began mass production of its PCIe 6.0-based PM1763 enterprise SSD in July 2026, featuring a newly developed 4nm controller and ninth-generation V-NAND, delivering more than twice the performance and over 1.8 times the power efficiency of its predecessor.
Samsung Electronics acknowledged at the 2026 JEDEC Forum, held alongside SEDEX 2026 at COEX in Seoul on Oct. 15, that standardizing next-generation AI memory faces challenges: customer-specific designs extend beyond the base dies of high-bandwidth memory (HBM) into DRAM core dies, making them increasingly difficult for memory manufacturers to manage. Hwang Ga-ram, a researcher on the product planning team of Samsung's Memory Business under its DS division, said LPDDR-PIM and zHBM have many customer-specific features that are extremely difficult to manage in actual production, and added that other memory manufacturers likely face the same challenges. Samsung's proposed zHBM architecture uses a 3D stacked structure that directly connects HBM to the computing processor, with TSVs distributed throughout DRAM core dies, so customized designs extend beyond the base die to the overall structure, presenting even greater standardization challenges than conventional 2.5D packaging. Hwang expressed hope that the LPDDR6-PIM standard would be established by the end of this year, and said not every function can be fully standardized while hoping JEDEC member companies could cooperate on common standards. Samsung also disclosed LPDDR5X-PIM development results: memory bandwidth is eight times that of conventional LPDDR5X; AI inference performance reached 102 TPS, approximately 3.8 times the 27 TPS of LPDDR5X, an improvement of about 23% over the 83 TPS demonstrated at Hot Chips in August; average power consumption was 11.5 watts, approximately 36% higher than the 8.4 watts of LPDDR5X; and inference performance per watt improved to 9 TPS/W, roughly 2.8 times the 3.2 TPS/W of conventional LPDDR5X.
Iron Device announced on Oct. 15 that it will join a government-backed research project led by South Korea's Ministry of Trade, Industry and Resources (MOTIR) to develop an on-device AI computing module for robotic hands. The project has a total budget of approximately 5.25 billion won and will run from August this year through the end of 2029. Iron Device will develop a low-power system-on-chip (SoC) integrating CPU, GPU and NPU, aiming to reduce the module's footprint by about 59% compared with Nvidia's Jetson Orin Nano while tripling power efficiency (TOPS/W) and cutting latency from sensor data to motor control to 20 ms or less. The company plans to sell the completed module to domestic and overseas humanoid and industrial robot customers independently of the project, targeting a reduction of customers' robot system costs by more than 25%.
British semiconductor IP company Arm said on Oct. 15 that it has developed a new CPU benchmarking framework for agentic AI, with support from Fujitsu, Meta and OpenAI, designed to evaluate real-world agentic AI workloads and performance across the entire computing process. Arm claimed that under the new framework its AGI CPU delivered approximately twice the task throughput per rack of AMD's fifth-generation EPYC Turin 9755 server CPU; the measurements were conducted by analyst firm Signal65 at Arm's request. The AGI CPU, unveiled in March, is Arm's first internally designed server CPU and was jointly developed with Meta. Arm said conventional CPU benchmarks and model inference metrics fail to capture CPU workload demands as AI agents grow. Meta is also adopting Arm's AGI CPU in its next-generation open server rack design, Yosemite YV5. The source does not state the cause; the comparison is Arm's claim, not independently verified.
Techwing said in a regulatory filing on Oct. 14 that preliminary third-quarter revenue reached approximately 87.8 billion won and operating profit about 18 billion won, year-on-year increases of 110.18% and 153.04% respectively, benefiting from a boom in the memory semiconductor market. Cumulative revenue for the first nine months of this year was approximately 197 billion won with operating profit of about 40.2 billion won, both already exceeding last year's full-year revenue of about 159.1 billion won and operating profit of approximately 15.8 billion won. The company attributed the growth to increased capital spending by Samsung Electronics, SK hynix and Micron, the three major memory chipmakers; as the three memory manufacturers expand their fabs and increase wafer production, demand for testing has grown and demand for memory test handlers has surged. Techwing supplies HBM testing equipment to all three companies, Micron is a major customer, and memory test handlers such as the TW350HT account for the largest share of the company's business. Revenue from a new product supplied to Samsung Electronics was also recognized in the third quarter; Techwing disclosed in August that it had been supplying HBM testing equipment worth 9.72 billion won to Samsung since June, confirmed to be its Cube Prober equipment. The Cube Prober is an HBM die testing system that performs comprehensive testing of logic and core dies and can test 256 dies simultaneously at temperatures ranging from minus 40 to 150 degrees Celsius; Techwing has been supplying Cube Prober equipment to Samsung Electronics since last year and also supplies it to SK hynix.
Sipeed announced its MaixStation, a Chinese-made rival to Nvidia’s DGX Spark and AMD’s Ryzen AI Halo, expected to cost around $3,999 for the 128GB model. The company said sign-ups are open ahead of a Kickstarter campaign set for the end of 2026, with units to ship within three months after the campaign closes. The NPU toolchain is due by the end of October 2026. The announcement was published on 15 October 2026.
TASKING has launched the winIDEA AI Kit, a set of tools and files that allows AI agents to integrate with TASKING's unified toolchain through the winIDEA development environment. The kit combines three maintained components: winIDEA MCP Server (providing structured access to design tool capabilities including debug control, memory, variables, breakpoints, trace, coverage, profiling, and timing analysis), AI-ready winIDEA SDK Documentation (assisting agents in generating accurate automation scripts), and Embedded-Development Skills (task-oriented guidance for debugging, timing analysis, winIDEA configuration, and device-specific workflows). During live debug sessions, AI agents can assist with pinpointing application crash locations, analyzing CPU load, inspecting variables/memory/processor states/breakpoints, configuring and analyzing trace, timing and code coverage, and automating timing coupling analysis in multicore systems to evaluate worst-case execution timing (WCET). The kit is model- and IDE-agnostic, supports cloud-based models and locally deployed LLMs, and is maintained alongside winIDEA releases. TASKING Co-CEO and CTO Christoph Herzog said AI is a tool to make engineers more productive, not replace them.
In a Power Corner interview, Jason Ngai, senior product marketing manager at pSemi, discussed the ARC1C0608, an LED backlight driver suited for single-cell (1S) Li-ion laptops that need a high conversion ratio from 2.7 to 5.5 V input to LCD backlight voltage of up to 30 V. According to Ngai, as modern SoCs have become highly efficient in standby, the display has become the dominant power draw, consuming up to 70% of total system power, and it cannot be put into standby—only dimmed or shut off. He explained that LED backlight drivers are boost converters whose efficiency worsens as input voltage falls: a typical 1S LED driver runs around the mid-to-high-80 percent range but drops as low as the mid-60s to mid-70s percent across the battery range (about 4.35 V fully charged down to about 3.2–3.6 V near cutoff). The ARC1C0608 uses a proprietary two-stage architecture combining a boost stage and a charge pump, achieving 95% peak efficiency and high-80s to over 90% efficiency across most of the operating range; in a 3.8-V input, 22–24 V output example, a 3x charge pump lets the boost stage reach only about 8 V. This reduces reliance on the inductor, enabling a low-profile solution with a 1.2-mm chip-size inductor (or 0.6-mm height with only about 1% efficiency loss). Beyond laptops, the IC is also suited for other single-cell display applications such as tablets, VR headsets, drone headlights, and bicycle displays.
Whose chips are really inside the hottest new products? We open them up and show you, one part at a time.
| Analog | $0.61 | n/a |
|---|---|---|
| Connector | $0.93 | n/a |
| CPU | $496.58 | n/a |
| DDR4 | $8.22 | n/a |
| DDR5 | $10.44 | n/a |
| MCU | $1.67 | n/a |
| MLCC | $0.01 | n/a |
| MOSFET | $0.94 | n/a |
| PMIC | $0.52 | n/a |
| SSD/HDD | $279.61 | n/a |