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[News] SK hynix Unveils H-TPU SSD Processor That Slashes Power Consumption, Eyes HBF Applications

What happened

According to ZDNet, SK hynix has unveiled its ultra-lightweight Hynix Transaction Processing Unit (H-TPU) architecture, dedicated to SSD data-plane control and transactions, distributing storage-control tasks across dozens of compact H-TPU clusters. According to Vice President Koo In-jae, who oversees SoC design, H-TPU eliminates complex CPU features such as superscalar and out-of-order execution and adopts a simplified four-stage pipeline, reducing processor area to approximately 4% and power consumption to around 2.5% of a conventional CPU core, activating only required modules. Building on H-TPU, SK hynix plans to introduce hardware automation (HWA), assigning repetitive storage-control tasks such as instruction processing, data address lookups, and temporary buffer copying to dedicated hardware circuits. SK hynix expects the H-TPU-based controller architecture to complement high-bandwidth flash (HBF), an emerging memory technology for AI workloads; AI inference is highly read-intensive with read-to-write ratios reaching approximately 300,000 to 1, and AI compilers and runtimes could inform the HBF SoC of upcoming data-processing needs for prefetching. Separately, according to Yonhap News, Samsung began mass production of its PCIe 6.0-based PM1763 enterprise SSD in July 2026, featuring a newly developed 4nm controller and ninth-generation V-NAND, delivering more than twice the performance and over 1.8 times the power efficiency of its predecessor.