Design the Right Chip: Why Prototyping Has to Be Easy

What happened

This is a technical article on FPGA prototyping; it contains no price, capacity, or supply-demand movement. Citing three Wilson Research Group functional verification studies, whose latest is the 2024 FPGA Functional Verification Trend Report, it states that between 2016 and 2024 'design error' as a root cause of ASIC functional flaws fell from 75% to 60% and 'changes in specification' fell from 59% to 43%, while 'incorrect or incomplete specification' went from 56% to 58% to 59% — essentially flat and slightly worse (each figure is the share of respondents citing that cause; multiple answers were allowed, so the numbers do not sum to 100%). The article argues FPGA prototyping can test 'are we building the right chip?' at the specification stage, and describes S2C's Prodigy platform and PlayerPro toolchain: 100+ Prototype Ready daughter cards and reference designs and 50+ Prototype Ready IP blocks; the Prodigy Logic System S8-100, built on the AMD Versal Premium VP1902, carries roughly 100 million ASIC gates per core module, two modules roughly 200 million, four roughly 400 million, with 2,212 XPIOs at up to 56Gbps. Company facts: S2C has spent more than 20 years on ASIC and SoC verification, has more than 300 employees, serves 700+ customers through seven branches and offices worldwide, and since 2020 has served 12 of the world's top 25 semiconductor companies; S2C estimates total cost of ownership runs 30–50% below the legacy EDA suppliers.

Impact and signal

Affected components and suppliers

Source and time

Source: SemiWiki · 10/15/2026 · View original source