Samsung Electronics Highlights Limits of AI Memory Standardization at JEDEC Forum

What happened

Samsung Electronics acknowledged at the 2026 JEDEC Forum, held alongside SEDEX 2026 at COEX in Seoul on Oct. 15, that standardizing next-generation AI memory faces challenges: customer-specific designs extend beyond the base dies of high-bandwidth memory (HBM) into DRAM core dies, making them increasingly difficult for memory manufacturers to manage. Hwang Ga-ram, a researcher on the product planning team of Samsung's Memory Business under its DS division, said LPDDR-PIM and zHBM have many customer-specific features that are extremely difficult to manage in actual production, and added that other memory manufacturers likely face the same challenges. Samsung's proposed zHBM architecture uses a 3D stacked structure that directly connects HBM to the computing processor, with TSVs distributed throughout DRAM core dies, so customized designs extend beyond the base die to the overall structure, presenting even greater standardization challenges than conventional 2.5D packaging. Hwang expressed hope that the LPDDR6-PIM standard would be established by the end of this year, and said not every function can be fully standardized while hoping JEDEC member companies could cooperate on common standards. Samsung also disclosed LPDDR5X-PIM development results: memory bandwidth is eight times that of conventional LPDDR5X; AI inference performance reached 102 TPS, approximately 3.8 times the 27 TPS of LPDDR5X, an improvement of about 23% over the 83 TPS demonstrated at Hot Chips in August; average power consumption was 11.5 watts, approximately 36% higher than the 8.4 watts of LPDDR5X; and inference performance per watt improved to 9 TPS/W, roughly 2.8 times the 3.2 TPS/W of conventional LPDDR5X.

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Source and time

Source: The Elec · 10/15/2026 · View original source