NuAxi Stream - Real-Time Semiconductor Intelligence

Thu, Oct 22

06:53Impact score 55
[News] Micron Reportedly Rules Out 4F² DRAM Scaling, Backs 6F² and 3D DRAM in Next-Gen Memory Roadmap
Micron is reportedly sticking with its 6F² DRAM architecture rather than adopting 4F², even as Chinese rival CXMT advances the alternative design. According to Nikkei, Scott DeBoer, Micron's president and chief technology and products officer, said during a recent technology webinar that 4F² is not 'on the roadmap right now' after more than 20 years of evaluation; the company plans to extend its 6F² architecture while developing 3D DRAM as a longer-term alternative. DeBoer explained that DRAM bit density is primarily determined by capacitor pitch rather than cell architecture alone, and pointed to fundamental scaling limitations, greater manufacturing complexity, and higher costs associated with 4F². Roadmap details: the 1γ (1-gamma) node is already in high-volume manufacturing and will underpin products introduced over the next 12 months; the next node, 1δ (1-delta), is expected to enter volume production in the second half of 2027, targeting a bit-density improvement in the mid-20% range, and will support next-generation memory products including DDR6, LPDDR6, HBM5, and vertical HBM (vHBM); the 1ε (1-epsilon) node is being developed with wafer bonding to improve bit density and support AI applications; for the subsequent 1ζ (1-zeta) and 1η (1-eta) nodes, the company is exploring High-NA EUV, new materials, and other innovations. 3D DRAM is placed between the 1ζ and 1η nodes in the roadmap, but development is proceeding in parallel with planar DRAM, with adoption depending on cost, manufacturing complexity, and device performance. On products, Micron is preparing DDR6 and LPDDR6, targeting twice the bandwidth of DDR5 and a 35% improvement in power efficiency over LPDDR5 respectively, with greater efficiency gains at certain densities; the company also plans a 1TB RDIMM following its recent sampling of a 512GB DDR5 RDIMM. For AI applications, Micron is advancing vHBM, which stacks memory directly on processing chips to deliver substantially higher bandwidth, developing it alongside standard and custom HBM products, although thermal management remains a challenge; packaging efforts include hybrid bonding, taller HBM stacks, and improved cooling technologies. For NAND, Micron plans to ramp its Generation 11 (G11) technology in the second half of 2027; G11 targets twice the bit density of G9 NAND, 1.5 times the I/O speed, and lower data-transfer energy consumption, and will adopt wafer-on-wafer bonding and feature more than 400 layers.
DRAM6F² DRAM3D DRAMMicronTrendForce
03:41Impact score 96
[News] PSMC Q3 Gross Margin Hits 48% on Memory Price Gains; Eyes 10–20% Mature-Node Price Hikes in 2027
PSMC's third-quarter revenue rose 23% sequentially and 80% annually to NT$21.3 billion, while net profit surged 98% and 338%, respectively, to NT$6.5 billion, with gross margin climbing 20 percentage points to 48%, driven by rising memory prices and tight foundry capacity. According to Liberty Times, PSMC President Martin Chu expects fourth-quarter revenue to grow by double digits sequentially as ASPs continue to rise; in the third quarter, completed memory wafers had ASPs more than 30% below those entering production during the same period, meaning recent price increases have yet to be fully reflected in revenue, with higher-priced wafers expected to contribute more in the fourth quarter. According to TechNews, global DRAM supply remains tight as major manufacturers shift capacity toward HBM and gradually exit specialty DRAM, keeping PSMC's specialty DRAM foundry prices elevated; PSMC is advancing its 1p DRAM collaboration with Micron, with a PDK due by the end of 2026, equipment arriving in 1Q27, and trial production starting in 2Q27. PSMC notes tight MLC NAND supply is driving demand for high-capacity SLC NAND, with the company shifting its SLC foundry platform to 24nm; AI servers require three to five times as much NOR Flash per system as conventional servers, and PSMC is the only NOR Flash foundry outside China. According to PSMC's earnings presentation, wafer input ASPs for its 8-inch and 12-inch logic foundry services rose 8–10% in the third quarter; with capacity constraints persisting, the company plans further price hikes of 10–20% in 2027 and is negotiating long-term agreements (LTAs) to secure pricing and volumes. PSMC has begun shipping 55nm BCD products with customers seeking three-year contracts; fully utilized 2026 foundry capacity is squeezing smartphone PMIC production, prompting major handset makers to seek 2027 capacity; 80% of 2027 MOSFET and IGBT capacity is already covered by LTAs; GaN products have entered small-volume wafer production pending final customer validation. IPD order visibility extends into 2028 with mass production underway on 8-inch and 12-inch wafers; WoW hybrid bonding small-scale trial production is underway with mass production targeted for 1H27. The Micron PWF project remains on schedule, with pilot line construction expected to finish by the end of 2026 and mass production planned for 4Q27.
memoryspecialty DRAMNAND FlashPowerchip Semiconductor Manufacturing Corporation (PSMC), MicronTrendForcePrice Movement
02:33Impact score 20
MCUs accelerate multimodal edge AI
Synaptics introduced the Astra SR200 series of xMCUs, which run multimodal AI workloads entirely on-device, combining heterogeneous, AI-native compute and acceleration with integrated high-bandwidth custom DRAM scalable to hundreds of Mbytes. The devices are powered by Synaptics' Torq AI engine with Google Research's transformer-capable Coral NPU and deliver up to 400 GOPS of AI inference. The series comprises three pin-compatible product lines: the SR210 reaches 200 GOPS for always-on voice and sensing; the SR230 adds vision, display, and optional audio at 300 GOPS; and the SR250 provides 400 GOPS with dual vision and display paths for demanding edge applications. The devices also feature Arm Cortex-M85 and Cortex-M52 cores, integrated vision and audio capabilities, and hardware-rooted security, with a tiered architecture pairing up to 8 Mbytes of SRAM with extensible, high-bandwidth custom DRAM that Synaptics says runs workloads at one-third the power of typical system DRAM.
multimodal edge AI xMCUSynapticsEDN
02:32Impact score 10
Processor IP brings generative AI to edge devices
BrainChip's Sequora processor IP core runs generative AI and large language models (LLMs) directly on battery-powered edge devices, such as earbuds and sensor nodes. It pairs with the company's Akida neural processor IP to handle complementary AI workloads: Akida processes streaming sensor data including vibration, audio, radar, raw RF IQ data, and biological signals, while Sequora runs generative and sequential AI tasks, from on-device LLM inference to voice-to-voice interaction and AI agents. Sequora is optimized for state-space models (SSMs), which maintain a fixed-size state to represent input history, keeping memory requirements constant regardless of sequence length, an architecture suited to generative AI workloads on resource-constrained edge devices. It uses a unified multiply-accumulate (MAC) array for both signal processing and neural-network computation, eliminating the need for a separate DSP preprocessing stage, and its instruction-set architecture (ISA) allows new algorithms to be deployed through software updates. Sequora is available now as licensable semiconductor IP, delivered as process-portable, fully synthesizable RTL; the package includes verification IP, synthesis scripts, and an SDK with a compiler, C++ runtime library, and model zoo.
Sequora processor IP coreAkida neural processor IPBrainChipEDN
02:30Impact score 60
[Breaking] Google Reportedly Sticks With Intel EMIB-T Despite 35% Substrate Yields as HumuFish Schedule Tightens
Google reportedly remains committed to Intel's EMIB-T for HumuFish despite poor substrate yields. According to industry sources, EMIB-T substrate yields were around 35% in 3Q26, well short of the 50% target set for year-end; the reported causes are thermal expansion differences between ABF substrates and embedded silicon bridges that make precise alignment difficult during high-temperature processing, and NCF (Non-Conductive Film) applied beneath the bridges' TSVs trapping air bubbles during bonding, potentially weakening adhesion. Despite market rumors of a HumuFish delay and the possibility of a switch to TSMC's CoWoS-L, supply chain checks indicate HumuFish remains '100%' committed to EMIB-T. Intel has adjusted its substrate electroplating process, and suppliers including Ibiden, Unimicron, and Shinko continue working to improve yields. Google's TPU v9 lineup is confirmed to include three variants: Broadcom-designed WhaleFish (expected to adopt TSMC's CoWoS-L, with mass production slated for 2H27), MediaTek-designed HumuFish (set for 1H28 mass production, relying exclusively on Intel's EMIB-T), and TriggerFish (also planned to use EMIB-T, with production targeted for 2H28 or later). Per TechNews citing analyst Ming-Chi Kuo, TriggerFish is positioned as an upgraded TPU v9 with stronger inference capabilities and features three key upgrades over HumuFish: 2–3 times the SRAM capacity, an additional simulation die, and a shift to HBM4E from HumuFish's HBM4. On delays, the tape-out of Google-designed Compute Die A, built on TSMC's N2 process, has been pushed back to late October while other dies remain on schedule, and the delay is expected to push back trial production of the complete package; Commercial Times further notes the MediaTek-involved Google TPU v9 project (HumuFish) could see its tape-out pushed back to January 2027 due to design revisions, potentially delaying shipments until 1Q28. With HumuFish not slated for mass production until 1H28, the supply chain still has time to address EMIB-T's remaining issues, but a tape-out slip to January 2027 could compress that cushion.
Intel EMIB-T substratesABF substratesNCF (Non-Conductive Film)Google, Intel and 8 totalTrendForce
00:30Impact score 60
[News] NVIDIA-Linked Groq Reportedly Eyes Shift From SRAM to 3D-Stacked DRAM for Next-Gen AI Chips
According to ZDNet citing industry sources, Groq, the AI chip company that licensed its inference technology to NVIDIA, is reportedly considering 3D-stacked DRAM for its next-generation chips, a potential shift away from its SRAM-centric design that could significantly increase on-chip memory capacity; this remains a reported plan/rumor, not a confirmed implementation. The report indicates Groq is exploring 3DS (3D Stacked Memory), which uses through-silicon vias (TSVs) to vertically connect DRAM dies; while both 3DS and HBM rely on TSVs, HBM focuses on high data transfer speeds while 3DS aims to increase memory capacity while retaining conventional DRAM interfaces. The existing NVIDIA Groq 3 LPX is a rack-scale AI inference accelerator designed for low-latency, large-context workloads on the Vera Rubin platform; according to NVIDIA, each Groq 3 LPU integrates 500MB of SRAM with 150TB/s of on-chip memory bandwidth, while a full LPX rack combines 256 LPUs to deliver 128GB of SRAM and 40PB/s of aggregate SRAM bandwidth; according to the company, each rack provides 12TB of DDR5 memory alongside 128GB of SRAM. According to 36Kr citing d-Matrix CEO Sid Sheth, SRAM capacity increases by only around 10–20% every two years while AI model sizes could double every six to nine months, making it increasingly difficult for SRAM alone to meet growing demands for memory capacity and bandwidth. On manufacturing, according to Seoul Economic Daily, Samsung Foundry produces NVIDIA's Groq 3 LPU using its 4nm process at its Pyeongtaek facility; Samsung executives said in June that the company was discussing foundry cooperation with NVIDIA on the next-generation Groq LPU, and TSMC Chairman C.C. Wei said during the company's April earnings call that TSMC was working with customers on next-generation LPU development. Separately, Cerebras, another AI chipmaker that relies heavily on SRAM, is also pursuing 3D-stacked DRAM; according to the company, its future CS-6 system will integrate stacked DRAM with wafer-scale SRAM and compute to significantly expand memory capacity while preserving fast data access.
SRAM3D-stacked DRAM (3DS)HBMGroq, NVIDIA and 6 totalTrendForce

Wed, Oct 21

23:30Impact score 58
ASML and other critical semiconductor equipment suppliers expedite shipments to Musk's Terafab
Elon Musk said on October 20, during a live broadcast of SpaceX's Q3 2026 earnings call on X, that ASML and other critical semiconductor equipment suppliers have expedited shipments to the Terafab semiconductor manufacturing facility, a joint megaproject between Tesla and SpaceX, to support his aggressive timeline. He said the company is targeting volume chip production at Terafab's primary facility in Gibbons Creek, Texas, by the third or fourth quarter of 2028, emphasizing that the timeline is highly aspirational and carries 'big error bars'; SpaceX plans to manufacture its first experimental test chip at its research fabrication facility in Austin, Texas, around Q2 2027. Terafab will use traditional extreme ultraviolet (EUV) lithography systems utilizing Intel's 14A manufacturing node; Intel officially joined the Terafab venture in April 2026 to co-develop and refactor silicon fabrication technology. According to unofficial sources, Terafab's first EUV tool was reportedly slated for delivery in mid-2027, and it remains unclear if this is the expedited timeline Musk referred to. Other major suppliers include Applied Materials, Lam Research, and KLA Corporation, as well as Japan's Tokyo Electron; Tesla and SpaceX are also in talks with about 10 South Korean equipment makers, including Hanmi Semiconductor (advanced packaging equipment) and HPSP (high-pressure hydrogen annealing equipment). Musk also outlined AI compute goals: 2.5 to 3 GW of computing capacity active by the end of 2026, a total of 13 GW by the end of 2027, and plans to bring a 440,000-GPU Nvidia 'Vera Rubin' training cluster online by the end of Q2 2027. The event remains a plan/target and volume production has not been achieved.
EUV lithography systemslogic chipsmemoryASML, Tesla and 11 totalTom's HardwareCapacity Change
21:25Impact score 30
Impulse Embedded Ltd Relaunches VELA: Powered by Advantech
Impulse Embedded Ltd has announced the relaunch of VELA: Powered by Advantech, a series of in-stock industrial PCs, GPU systems and servers ready to build from the UK. The systems are configured and tested by Impulse Embedded in the UK using Advantech industrial computing hardware, with customer-selectable options for processor, memory, storage, graphics, operating system, expansion and I/O. The range is split into four tiers: VELA IPC for general industrial computing, with configurations that can include 13th Gen Intel Core processing and industrial DDR4 memory; VELA Performance, which can combine 13th Gen Intel Core i7 or Core i9 processing with up to 128GB of industrial DDR4 memory and up to 2TB of PCIe Gen4 NVMe storage, plus RAID storage options; VELA GPU for workloads relying on dedicated graphics or parallel processing such as AI model training, AI inference and machine vision, in tower and 4U configurations; and VELA Server for server-class processing, available in tower, 1U, 2U and 4U formats with networking options extending up to 100GbE and selected configurations supporting registered DIMM memory, RAID storage and redundant power supplies. The two companies have worked together for more than 20 years. The source does not state a specific cause for the relaunch beyond the stated aim of offering customers configurable systems around their exact requirements without lengthy lead times.
industrial PCsGPU systemsserversImpulse Embedded Ltd, AdvantechEE Journal
21:10Impact score 50
Samsung Electro-Mechanics signs KRW 360.5bn memory substrate supply deal
Samsung Electro-Mechanics has signed a long-term supply agreement to provide package substrates for memory semiconductors to an unnamed global customer throughout 2027, in a deal worth KRW 360.5 billion (approximately USD 271 million), covering the period from January 1 to December 31, 2027. According to a press release from Samsung Electro-Mechanics, this is the first major order of this kind for its Package Solution Unit; its Component Solution Unit has signed similar agreements since May for silicon capacitors, MLCCs for AI servers and high-performance inductors. With this order, the company has signed seven long-term supply agreements since May 2026 that were large enough to require public disclosure, meaning each worth at least 2.5% of the company's sales, together totaling KRW 4.3 trillion (USD 3.2 billion). The company points to generative AI and high-performance computing increasing demand for high-bandwidth memory (HBM) and high-performance server DRAM modules, and notes that as memory chips become faster and more densely integrated, substrates connecting them to the main board need more layers, finer circuits and thinner designs. The company plans to expand long-term agreements with major customers to reduce exposure to volatile business cycles and says it will build closer supply cooperation and a stable supply system for the package substrate business as AI and HPC demand grows.
package substrates for memory semiconductorshigh-bandwidth memory (HBM)high-performance server DRAM modulesSamsung Electro-MechanicsEvertiqPartnership/M&A
21:00Impact score 30
Arteris FlexGen Opens Up Multi-Die Traffic Management for Non-Coherent Networks
Arteris has introduced the FlexGen Multi-Die solution, extending multi-die traffic management to non-coherent networks. While the previously introduced Arteris Ncore Multi-Die solution addressed coherent traffic across chiplets, FlexGen Multi-Die now addresses the even more common requirement of non-coherent traffic: by tunneling the NoC protocol through the UCIe link, it automatically extracts QoS management information, carries it as sideband signals, and reconstructs it into the NoC on the other chiplet, making the chiplet-to-chiplet interface transparent and preserving inter-chiplet traffic policy management. Rick Bye, Director of Product Management and Marketing at Arteris, said the solution is very configurable and largely agnostic to the PHY IP a designer uses; Arteris is already working with several companies that have their own PHY IP, most notably AMD, which provided an enthusiastic endorsement, and over time Arteris also expects to qualify this new capability with some commercial UCIe IP options. Additionally, FlexGen Multi-Die can enable more efficient use of UCIe IP: for chiplet pairs where both sides can initiate and be targets (a scenario seen when replicating chiplets each containing an XPU and memory), some AXI-to-UCI bridges require two UCIe ports per chiplet, whereas FlexGen Multi-Die manages that traffic up to bandwidth limitations and is more area, power, and I/O efficient. This is a product technology write-up with no price, capacity, or supply-demand data.
Network on Chip (NoC) IPUCIe IPAXI-to-UCIe bridgeArterisSemiWiki
19:18Impact score 60
Fujifilm Prepares for EUV Photoresist Mass Production in Pyeongtaek, Deepens Samsung Ties
Japan's Fujifilm is expanding its extreme ultraviolet (EUV) photoresist production capacity to deepen cooperation with Samsung Electronics. Brian O'Donnellley, president of Fujifilm Electronic Materials USA, said the company is producing EUV photoresists in Pyeongtaek and, although it has not yet entered full-scale mass production, some EUV PR products have passed qualification tests at major customers. Fujifilm has expanded EUV PR production facilities in Shizuoka, Japan (its primary hub for advanced photoresist development and production) and Pyeongtaek, South Korea (near Samsung, selected for its most advanced products); EUV PR production and inspection equipment at both locations began operating in October 2025. The source does not state when full-scale mass production in Pyeongtaek will begin. The company cited artificial intelligence (AI) driving demand for materials used in processes at 2 nanometers and below, and expansion of advanced manufacturing processes increasing demand for ArF and EUV photoresists as the stated reason. Separately, Fujifilm is expanding its CMP slurry production facility near Samsung's Cheonan campus, planning to increase production capacity by approximately 30%, with additional facilities scheduled to begin operating in the first half of 2027; Fujifilm holds the largest global market share in CMP slurries for copper interconnects. The company also operates a facility in Carrollton, Texas near Samsung's Taylor plant and is considering various options to expand its manufacturing presence in South Korea, where it currently has two production facilities.
EUV photoresistArF photoresistCMP slurryFujifilm, Samsung ElectronicsThe ElecCapacity Change
17:02Impact score 25
(PR) Synaptics Announces Astra SR200 Multimodal Edge AI Processors with Google Coral NPU
Synaptics Incorporated (Nasdaq: SYNA) introduced the Astra SR200 Series, launching the xMCU, a new class of microcontrollers that runs multimodal Edge AI. The xMCU combines heterogeneous, AI-native compute and acceleration with integrated high-bandwidth custom DRAM scalable to hundreds of megabytes, which the company says enables larger AI models and richer multimodal workloads to run entirely on-device. The SR200 Series is designed for the next generation of AI wearables, battery-powered sensing devices, connected cameras, streamers, and industrial vision and voice systems. It is powered by the Synaptics Torq AI engine, features the Coral NPU from Google Research, and includes the industry's first pairing of the Arm Cortex-M85 and Cortex-M52, together with integrated vision and audio capabilities and hardware-rooted security. This is a product announcement and does not involve price or supply-demand changes.
Astra SR200 Series multimodal Edge AI processors (xMCU)SynapticsTechPowerUp
15:57Impact score 60
Samsung, SK Hynix reportedly upgrading China NAND fabs to fend off YMTC amid softening US stance
Samsung Electronics and SK Hynix are upgrading their NAND flash factories in China to make chips with more than 200 layers, Reuters reported on October 21, citing four people familiar with the plans. According to the report, the move would let the South Korean memory makers win back ground lost to Yangtze Memory Technologies Co (YMTC), even though US curbs on upgrading their China operations remain formally in place. This is a reported plan under way; no completion timeline is given and the US restrictions have not been lifted.
NAND flashSamsung Electronics, SK Hynix and 3 totalDigiTimes AsiaCapacity Change
15:53Impact score 72
Micron's Taichung union deal eases Taiwan DRAM strike risk; Taoyuan dispute remains unresolved
With a strike by Micron Taiwan employees looming, Micron Technology said that Micron Memory Taiwan and the Taichung chapter of the Taiwan Micron Memory Union had reached agreement on several issues after multiple rounds of constructive discussions. The two sides signed a labour-management agreement and agreed to withdraw the mediation scheduled for October 22. However, the Taoyuan union has planned a one-day strike for that same date (October 22), and Micron will continue talks with it. The source does not state the cause of the labour dispute.
DRAMMicron Technology, Micron Memory TaiwanDigiTimes AsiaDisaster/Disruption
12:41Impact score 58
CXMT's next DRAM milestone: 4F² server memory with hybrid bonding by end-2026
Chinese DRAM maker CXMT's next DRAM milestone is a plan to achieve 4F² server memory using hybrid bonding by end-2026. At a recent shareholder meeting, management pledged to enter what it called the 'uncharted territory' of extreme memory scaling, and stated it would use process innovation to overcome technical barriers. The milestone remains a stated plan; the source does not state any progress beyond the roadmap, the cause, or market impact.
DRAM4F² server memoryCXMTDigiTimes AsiaCapacity Change
11:24Impact score 60
China Smartphone Shipments Fall Around 15% as Memory Costs Drive Up Prices
China smartphone shipments fell around 15%. The source states the cause: higher component costs (memory costs driving up smartphone prices) and longer replacement cycles weakened China's smartphone market. Meanwhile, Huawei recorded double-digit shipment growth.
memoryHuaweiEE Times Asia
10:40Impact score 60
Memory costs weaken e-reader demand as E Ink cuts 2026 outlook
Surging memory prices are forcing e-reader makers to raise product prices, weakening demand and clouding E Ink Holdings' 2026 outlook. E Ink has cut its revenue-growth forecast, while Netronix expects shipments to remain flat. The companies are looking to electronic shelf labels, advertising displays, and products to offset pressure on consumer electronics.
memorye-readerselectronic shelf labelsE Ink Holdings, NetronixDigiTimes Asia
09:23Impact score 50
Samsung Electro-Mechanics wins KRW360.5 billion memory substrate deal as AI demand drives expansion
Samsung Electro-Mechanics has secured a long-term contract worth KRW360.5 billion (US$271.8 million) to supply package substrates for memory semiconductors. The source describes this as strengthening its position in the growing AI server component market.
memory semiconductor package substratesSamsung Electro-MechanicsDigiTimes Asia
09:20Impact score 60
Memory chip inflation accelerates smartphone brands' retreat from low-end devices
Rising memory prices are squeezing smartphone makers and consumers, pushing third-quarter smartphone shipments to their lowest third-quarter level since 2012, and accelerating the market's retreat from entry-level devices. Brands are raising prices, cutting low-margin models, and limiting production, while delayed upgrades and interest in used and refurbished phones further weigh on demand. The source does not state the cause of the memory price increase.
memory chipsentry-level smartphonesDigiTimes AsiaPrice Movement
09:15Impact score 0
Breaking AI's memory wall: former TSMC VP charts a path with HBM, optical links and 3D stacking
A background technical analysis notes that AI processor performance continues to improve, but memory bandwidth is growing more slowly, making data supply a major constraint on AI chip performance and energy efficiency. Efforts to shorten the distance between memory and compute units and increase die-to-die interconnect density are driving advances in HBM, advanced packaging and 3D integration. The article is an industry trend discussion and involves no specific manufacturer, price movement, capacity event or policy action.
HBMadvanced packaging3D integrationDigiTimes Asia

Analog	$0.68	−5.9%
Connector	$0.75	+0.2%
CPU	$386.74	−21.3%
DDR4	$88.40	−0.2%
DDR52026-W13	$14.89	−11.2%
GPU	$478.20	+8.2%
MCU	$0.68	−61.7%Unusual
MLCC	$0.01	+54.0%Unusual
MOSFET	$0.12	−82.8%Unusual
PMIC2026-W13	$0.44	−12.5%
SSD/HDD	$288.43	n/a

NuAxi Stream - Real-Time Semiconductor Intelligence

Thu, Oct 22

[News] Micron Reportedly Rules Out 4F² DRAM Scaling, Backs 6F² and 3D DRAM in Next-Gen Memory Roadmap

[News] PSMC Q3 Gross Margin Hits 48% on Memory Price Gains; Eyes 10–20% Mature-Node Price Hikes in 2027

MCUs accelerate multimodal edge AI

Processor IP brings generative AI to edge devices

[Breaking] Google Reportedly Sticks With Intel EMIB-T Despite 35% Substrate Yields as HumuFish Schedule Tightens

[News] NVIDIA-Linked Groq Reportedly Eyes Shift From SRAM to 3D-Stacked DRAM for Next-Gen AI Chips

Wed, Oct 21

ASML and other critical semiconductor equipment suppliers expedite shipments to Musk's Terafab

Impulse Embedded Ltd Relaunches VELA: Powered by Advantech

Samsung Electro-Mechanics signs KRW 360.5bn memory substrate supply deal

Arteris FlexGen Opens Up Multi-Die Traffic Management for Non-Coherent Networks

Fujifilm Prepares for EUV Photoresist Mass Production in Pyeongtaek, Deepens Samsung Ties

(PR) Synaptics Announces Astra SR200 Multimodal Edge AI Processors with Google Coral NPU

Samsung, SK Hynix reportedly upgrading China NAND fabs to fend off YMTC amid softening US stance

Micron's Taichung union deal eases Taiwan DRAM strike risk; Taoyuan dispute remains unresolved

CXMT's next DRAM milestone: 4F² server memory with hybrid bonding by end-2026

China Smartphone Shipments Fall Around 15% as Memory Costs Drive Up Prices

Memory costs weaken e-reader demand as E Ink cuts 2026 outlook

Samsung Electro-Mechanics wins KRW360.5 billion memory substrate deal as AI demand drives expansion

Memory chip inflation accelerates smartphone brands' retreat from low-end devices

Breaking AI's memory wall: former TSMC VP charts a path with HBM, optical links and 3D stacking

Chip Teardown Lab2 opened

Component price indexNPI, vs. prior period

Trending components