[News] NVIDIA-Linked Groq Reportedly Eyes Shift From SRAM to 3D-Stacked DRAM for Next-Gen AI Chips

What happened

According to ZDNet citing industry sources, Groq, the AI chip company that licensed its inference technology to NVIDIA, is reportedly considering 3D-stacked DRAM for its next-generation chips, a potential shift away from its SRAM-centric design that could significantly increase on-chip memory capacity; this remains a reported plan/rumor, not a confirmed implementation. The report indicates Groq is exploring 3DS (3D Stacked Memory), which uses through-silicon vias (TSVs) to vertically connect DRAM dies; while both 3DS and HBM rely on TSVs, HBM focuses on high data transfer speeds while 3DS aims to increase memory capacity while retaining conventional DRAM interfaces. The existing NVIDIA Groq 3 LPX is a rack-scale AI inference accelerator designed for low-latency, large-context workloads on the Vera Rubin platform; according to NVIDIA, each Groq 3 LPU integrates 500MB of SRAM with 150TB/s of on-chip memory bandwidth, while a full LPX rack combines 256 LPUs to deliver 128GB of SRAM and 40PB/s of aggregate SRAM bandwidth; according to the company, each rack provides 12TB of DDR5 memory alongside 128GB of SRAM. According to 36Kr citing d-Matrix CEO Sid Sheth, SRAM capacity increases by only around 10–20% every two years while AI model sizes could double every six to nine months, making it increasingly difficult for SRAM alone to meet growing demands for memory capacity and bandwidth. On manufacturing, according to Seoul Economic Daily, Samsung Foundry produces NVIDIA's Groq 3 LPU using its 4nm process at its Pyeongtaek facility; Samsung executives said in June that the company was discussing foundry cooperation with NVIDIA on the next-generation Groq LPU, and TSMC Chairman C.C. Wei said during the company's April earnings call that TSMC was working with customers on next-generation LPU development. Separately, Cerebras, another AI chipmaker that relies heavily on SRAM, is also pursuing 3D-stacked DRAM; according to the company, its future CS-6 system will integrate stacked DRAM with wafer-scale SRAM and compute to significantly expand memory capacity while preserving fast data access.

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Source: TrendForce · 10/21/2026 · View original source