FPD-Link camera bandwidth: from input lanes to line deadlines and DMA

1. Give every port an explicit interface contract

For each sensor, record active dimensions, frame rate, bit depth, actual CSI data type, packets per line, embedded data, lane count and HS rate, then Htotal/Vtotal, continuous or discontinuous clock and synchronization. RAW12 is a pixel-packing format, not a guarantee of continuous transmission at twelve times the pixel clock. Establish the actual burst pattern from the sensor mode table or captures.

The pairs below have explicit TI documentation, but do not approve arbitrary resolutions, clocks or cables. In particular, the 962's four RX inputs and single CSI output, and the 936's two RX inputs with replication, must not be mistaken for the 960's two independently routable outputs because of similar names or packages.

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2. Pass each input's limits before considering aggregation

DS90UB935-Q1 datasheet section 5.3, footnote 4, specifies up to 832 Mbps per CSI-2 data lane with one or two lanes, and up to 632 Mbps per lane with four lanes, for 2.528 Gbps combined. Two 800 Mbps lanes therefore provide 1.6 Gbps of input line capacity, not a shared 832 Mbps limit. Conversely, four 800 Mbps lanes do not meet the 935 four-lane condition. A low average payload does not excuse an excessive instantaneous HS lane rate.

Do not turn the 935's '3 Gbps' title into an exact encoded line rate. Section 6.3.2 describes a forward transmitter capable of up to 4.16 Gbps; actual line rate also depends on synchronous/asynchronous operation and reference clock. Aggregate CSI input bandwidth, the serial rate including encoding/control information, and usable video payload are different quantities. Apply the datasheet relationships for the same clock configuration rather than substituting one for another.

DS90UB913A-Q1 receives parallel LVCMOS, not MIPI CSI-2: PCLK is up to 100 MHz for a 10-bit payload and 75 MHz for 12-bit. With the 962, use a compatible RAW mode and verify that mode's PCLK subrange, HS/VS restrictions and 2.5 Mbps back channel. Do not borrow the 962's 12-bit 100 MHz condition for other serializers and apply it to 913A. The 935, 962, 913A and 936 are AEC-Q100 Grade 2, −40 to +105°C ambient. The reviewed material explicitly lists Functional Safety-Capable for 935 and 962; this classification is not established here for 913A/936 and is not system ASIL certification.

3. Find backlog along the pipeline rather than adding Gbps

The deserializer decodes each FPD-Link input into its RX buffer, then the CSI aggregator reads and transmits according to the forwarding mode. Best-effort round robin services buffers with valid data; synchronized forwarding imposes synchronization requirements on enabled inputs. Do not assume that a busy output automatically pauses a remote sensor or that an RX buffer can store a whole frame without a capacity specification.

Active-pixel rate W×H×fps×bpp describes average useful image data. Htotal/Vtotal describe sensor timing; they do not imply that every blanking pixel is sent as RAW data on CSI. For each active line, calculate the arrival interval, actual long/short packets and HS/LP overhead. Vertical blanking can lower average traffic, but if every active line adds backlog, prove that the buffer can hold the accumulated data instead of assuming a safe drain at frame end.

A virtual channel identifies a stream; it adds no physical bandwidth and does not synchronize exposures. Identical VC-IDs from multiple sensors need supported deserializer remapping that agrees with the SoC's VC/data-type filters. Synchronized forwarding also requires checking line cadence, format and behavior when an input disappears, not merely connecting frame-sync signals.

4. Example: why a 3.2 Gbps output can fail a 2.986 Gbps average load

Assume four identical synchronized 1920×1080, 30 fps RAW12 sensors, one long packet per active line and Vtotal=1125. Each uses a DS90UB953-Q1 with separately checked input conditions into a DS90UB960-Q1, and all four are routed to one CSI output with four lanes at 800 Mbps/lane. This is a 960 example, not a forced claim that the 962 supports this 1080p configuration. Each stream contains 0.746496 Gbps, or 2.985984 Gbps total active pixels, apparently below the 3.2 Gbps output.

TI SDAA236B, revised July 2026, section 5.2 Table 5-1 gives 0.93 µs of default DS90UB960 CSI transmitter overhead at 800 Mbps/lane with continuous CSI clock, 0x33[1]=1. With separate long packets for each input line and LP/HS transitions between packets, the four-packet lower bound is 4×(23040/(3.2×10⁹) seconds + 0.93 µs)=32.52 µs. Long-packet headers/CRC, short packets and metadata are still excluded, yet this already exceeds the 1/(30×1125)=29.6296 µs line interval.

The 0.93 µs value is not universal to FPD-Link or CSI-2 transmitters, nor does it describe discontinuous clock; the same table gives 2.06 µs at 800 Mbps with discontinuous clock. The result rejects this line-service contract and rules out approval from the average ratio alone. It is not a measured claim that every buffer depth, arrival phase or register configuration must lose frames.

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5. Faster lanes, routing or concatenation each change the contract

Do not begin by blindly shortening D-PHY timing. Check whether the SoC accepts a higher lane rate, whether the 960's second independently routable output is available, and whether a sensor mode can reduce line-arrival load. Under the same four-lane, 800 Mbps/lane, default continuous-clock conditions, two streams per output reduce the pixel-plus-transition lower bound to 16.26 µs per port. Add packet overhead and verify the second CSI receiver and concurrent DMA before approving it.

Line concatenation can combine four symmetric video lines into one long packet, paying the corresponding transition overhead once. In this example its pixel-plus-transition lower bound is 28.8+0.93=29.73 µs, still slightly above 29.6296 µs; concatenation is not an automatic fix. It also changes the line width/frame layout seen by the receiver, requires synchronization and symmetric formats, and needs a driver that understands the result. Replication adds receivers for the same data and cannot substitute for routing independent traffic.

If adjusting TLPX, THS-PREPARE, THS-ZERO or related parameters, meet both transmitter and target-SoC receiver requirements and validate voltage, temperature, channel length and errors. A temporary image is not production margin. Recompute overhead and buffering after changing clock mode, embedded lines or forwarding.

6. After CSI reception, budget unpacking and DMA

For the same four-stream example, storing packed RAW12 active pixels requires at least 2.985984/8=373.248 MB/s of writes. If the CSI receiver expands every pixel to 16 bits, this becomes 4×1920×1080×30×2=497.664 MB/s. These are decimal MB/s, excluding stride alignment, metadata, cache maintenance, display and ISP traffic. A full-image memory copy that reads and writes the expanded frame adds two image streams of memory traffic beyond capture writes.

These figures are general system arithmetic, not a throughput guarantee for a particular SoC. Budget each queue from actual stride×stored lines×fps, and verify VC-to-DMA context mapping, separate handling of embedded lines, buffer ownership and drop policy. Adequate total memory bandwidth does not prove that an individual CSI FIFO survives short arbitration stalls; observe overflow, frame sequence and timestamps with concurrent ISP, CPU and display traffic.

7. Freeze the mode table and end-to-end acceptance checklist

Version the calculation inputs, register readbacks and capture results together. This is an engineering acceptance plan, not TI certification of an untested sensor/SoC combination; physical-link LOCK is only the first layer of status.

• Record active pixels, Vtotal, line/short/embedded packets and actual HS lane rate; check 935 limits separately: 832 Mbps per lane for 1/2 lanes, 632 Mbps for 4 lanes.
• Save full serializer/deserializer identifiers and clock modes; match 913A parallel PCLK/width to the 962 RAW configuration.
• Calculate each input and each CSI output's line-service time; identify default/tuned timing, clock mode and forwarding, without transferring 0.93 µs across devices.
• Read back the actual 962 single-port, 936 replication or 960 routing configuration; do not count copies as new useful throughput.
• Check VC/data type, received dimensions, RAW packing and stride; verify exposure timing after synchronization, not just matching frame rates.
• Count frames, CRC/ECC errors, FIFO overflows and application timestamps under full DMA/ISP/memory load; validate counters and image content together.
• Exercise one-link loss, one-sensor restart, asynchronous phase drift and supply disturbances; define dropped-frame flags, resynchronization deadlines and whether other cameras continue.

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