Automotive Ethernet and FPD-Link: distinguish network endpoints from camera links

1. The devices serve different endpoints and are not interchangeable by line rate

An Ethernet design needs a MAC on the processor side, connected through one of the PHY's supported MII/RMII/RGMII/SGMII interfaces. A PHY alone does not provide the protocol stack, packetization or switching function. An FPD-Link camera path instead commonly feeds sensor CSI-2 into DS90UB953-Q1, crosses the serial link and exits the deserializer as CSI-2 to the processor. Similar cable construction or Gbps units do not make these links interoperable.

Sending an FPD-Link camera stream onto Ethernet requires a compute or bridge node that accepts CSI-2, processes/packetizes the data and has an Ethernet MAC. Buffering, latency, any compression and clock synchronization become system responsibilities. Replacing an FPD-Link deserializer with a DP83 PHY does not perform that protocol conversion.

2. Compare protocol, host interface and aggregation model

The table lists candidate architectures, not replacement guarantees. Distinguish a single Ethernet port, one camera's serial link and the CSI output after multi-camera aggregation. Their bottlenecks occur at different boundaries, so a single rate column cannot rank them meaningfully.

Scroll wide tables horizontally; column headers remain visible within the table.

3. Moving from 100BASE-T1 to 1000BASE-T1 is a system change

This guide uses the verifiable full device name DP83TC812S-Q1. Its cable side is 100BASE-T1; a host interface named RGMII or SGMII does not make the cable link gigabit. DP83TG720S-Q1 is 1000BASE-T1 and supports RGMII/SGMII on the host side. A processor with only MII or RMII cannot gain a gigabit link merely by replacing its PHY. The link partner must also support the target Ethernet physical layer.

TI describes a shared-board approach with required BOM changes, not a universal replacement promise for existing boards. For example, DP83TG720S datasheet section 8.4 compares DP83TC811 and DP83TG720 and identifies role changes such as EN/VSLEEP and DNC/VDD1P0. Before reusing a layout, check supplies, straps, reset, MAC timing and the analog front end pin by pin rather than matching only the 36-pin package outline.

Review the driver as well: explicitly configure the PHY identifier, initialization registers, master/slave or leader/follower roles, sleep/wake flow and diagnostic interpretation. DP83TC812S TC-10 capability does not establish identical low-power behavior across all DP83 devices. Validate one link under full load and sleep recovery before joining the switched network, keeping PHY, MAC and switching-software faults distinguishable.

4. FPD-Link requires explicit serializer pairing and output topology

The explicit pairs here are DS90UB953-Q1 with DS90UB954-Q1 and DS90UB953-Q1 with DS90UB960-Q1; TI documentation for both deserializers lists DS90UB953-Q1 compatibility. This does not establish compatibility with every FPD-Link serializer. Still verify input data types, serial-link rate, reference clock, back-channel control and sensor initialization for the selected operating mode.

DS90UB954-Q1 aggregates one or two sensors. Its replicated-output mode in the 2-lane configuration creates two copies of the same aggregated stream, not additional independent image throughput. DS90UB960-Q1 is a sensor hub with up to four inputs and two CSI-2 output ports, supporting configured routing or replication. Four cameras need their respective serial links; one serializer serving all four is not the default architecture. The 960 is AEC-Q100 Grade 2 with a −40 to +105°C ambient range, not a Grade 1-temperature device merely because it is automotive.

5. Keep separate budgets for pixels, serial line rate and CSI output

The DS90UB960-Q1 description of four 4.16 Gbps links refers to each FPD-Link input's serial line rate. It is neither a 4.16 Gbps whole-device image payload rating nor permission to treat 4 × 4.16 Gbps as usable output throughput. Account for line encoding, packetization and output-port capacity separately. CSI-2 usable bandwidth also depends on LP/HS transitions, continuous/discontinuous clock, line length and forwarding mode; datasheet section 7.4.20 addresses these overheads.

Worked example: 1920 × 1080 at 60 frames/s and 12 bits/pixel yields 1.493 Gbps of active pixels per camera, or about 5.972 Gbps for four. This excludes transmitted metadata, packet overhead and timing margin. A CSI output configured for four lanes at 1.6 Gbps has 6.4 Gbps of nominal line capacity, but 5.972 being less than 6.4 is not sufficient proof of feasibility. Validate actual line timing, forwarding mode and processor reception. If both ports replicate the same data, do not count the duplicate as new useful bandwidth.

The same example shows why gigabit Ethernet is not an automatic replacement for a raw camera link: one camera's active pixels already exceed 1 Gbps before Ethernet overhead. An Ethernet transport design must revisit resolution, frame rate, compression or network capacity and account for the resulting computation and latency. These calculations expose bottlenecks; they do not guarantee support for an arbitrary sensor combination.

6. Go beyond link lock to end-to-end acceptance

Ethernet link-up or FPD-Link lock is only the start of layered debugging. Ethernet still needs packets reaching the application; FPD-Link still needs complete frames, correct timing relationships and no processor overflow. Start with device BIST, test patterns or loopback to isolate the physical path, then attach the real MAC or sensor and retain error counters, timestamps and recovery logs.

• Label every Ethernet MAC/PHY or CSI-2/serializer/deserializer boundary and identify any unimplemented protocol conversion.
• Check full device names and link partners: DP83TC812S is 100BASE-T1 and DP83TG720S is 1000BASE-T1; equal footprints do not approve substitution.
• Check MAC voltages, clock/delay settings, straps, management address, rails and reset sequencing, including recovery after sleep.
• Fix the verified 953+954 or 953+960 pairing and mode; check sensor data types, I2C address mapping and synchronization signals.
• Evaluate the target harness, connectors and aging/temperature corners; PoC also needs current, voltage-drop and filter analysis, not an assumption of integrated power delivery.
• Budget each input and CSI output using actual pixels, frame rate, bit depth and packet timing; verify virtual channels and processor lane/port configuration.
• Test DS90UB960 bandwidth distribution separately from replication; design to its Grade 2, −40 to +105°C ambient limits.
• Under full load, cable reconnection, single-camera reset and supply disturbances, record application-data continuity, error counters and resynchronization time.

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