TrendForce posted at 12:00 PM on Oct 28, 2026 that Google's TPU push is gaining momentum: OpenAI reportedly plans to buy Google TPUs, and Oracle plans to bring TPUs to its cloud in 2027. TrendForce raises the question of whether this could challenge NVIDIA's dominance. Both items remain reported plans/rumors rather than confirmed or implemented transactions. The source does not state the cause.
TPUGoogle, OpenAI and 4 totalTrendForce Official (Market Data)Partnership/M&A
Oracle has signed partnerships with Cerebras and other chipmakers to host their chips in its cloud infrastructure. The Cerebras deal gives the chipmaker a new large customer to anchor its post-IPO trajectory, while allowing Oracle to reduce its reliance on Nvidia's expensive chips; even so, Oracle also announced a purchase of Vera Rubin platforms for its data centers.
AI chipsCerebras chipsVera Rubin platformsOracle, Cerebras and 5 totalDigiTimes AsiaPartnership/M&A
Alongside its quarterly results, SK Hynix said it expects memory shortages to persist until at least the year 2030, attributing this to AI-driven demand growth outpacing supply, the technical difficulty of leading-edge processes, and the long lead time required to build new production facilities. The company has 14 long-term deals with 14 big buyers, who will collectively buy more than half of its output during 2027 and 2028, and some of them want to extend the agreements; the deals include a mechanism that reflects market conditions within a price range agreed upon with customers. These deals helped SK Hynix record quarterly revenue of ₩104.6 trillion ($78.1 billion), up 328 percent year-over-year and 32 percent quarter-over-quarter, with operating profit of ₩87.68 trillion ($62.8 billion), up 486 percent year over year. The company outlined plans to expand production, including increasing HBM4 output, which it believes will surpass HBM3E in both shipment volume and revenue in the fourth quarter and become a mainstream product; rapidly increasing the portion of its 10nm-class 6th generation (1c) process technology and expanding sales of DDR5 and LPDDR5 SOCAMM for AI servers; and developing NAND based on HBF. Chief financial officer Kim Woo-hyun predicted that shipment volumes for PCs and mobile devices are expected to decrease due to cost burdens from rising memory prices and supply shortages. The company's share price rose about three percent in after-hours trading.
Google's tensor processing unit (TPU) business has gained one confirmed and one reported major customer within a week: Oracle is the confirmed customer and OpenAI is reportedly next. This adds pressure on Nvidia, whose graphics processors still dominate AI computing even as its biggest buyers look for alternatives.
Google TPUNvidia graphics processorsGoogle, Nvidia and 4 totalDigiTimes Asia
Anthropic disclosed details of its computing partnerships with Google, Amazon Web Services (AWS), Microsoft, Advanced Micro Devices (AMD) and other providers in its S-1 filing for an initial public offering (IPO), revealing distinct cooperation models and chip technologies across its partner ecosystem. Per the title, Anthropic's surging compute demand fuels ASIC prospects, favoring Broadcom over MediaTek.
Google recently unveiled its flagship AI model, Gemini 4 Argon. The model consumed an unprecedented 25 trillion tokens within 72 hours of launch—three times the volume recorded by Gemini 3.0 over the same timeframe, setting a new record for the company. In his first in-depth public interview since the release, Google CEO Sundar Pichai addressed market skepticism regarding claims that 'Google has abandoned frontier AI' and outlined Google's strategy for allocating AI compute resources, managing its cloud business, and deploying long-term infrastructure. The source title indicates that Google prioritizes frontier AI as cloud capacity runs short.
AI compute capacitycloud capacityGoogleDigiTimes Asia
Semiconductor IP company Chips&Media disclosed its third-quarter 2026 results on Oct. 27, reporting consolidated revenue of 7.162 billion won, up 8.2% year on year, and operating profit of 1.657 billion won, up 8.7% year on year. Growth was driven by IP licensing revenue: third-quarter licensing revenue rose 33% year on year to 4.431 billion won. The company secured its first licensing contract related to a domestic on-device AI semiconductor project, won a new automotive project from a major South Korean fabless chipmaker, signed new licensing agreements with Chinese customers for AI SoCs and humanoid robots, and signed a new mobile licensing agreement with existing customer Google. Royalty revenue, however, fell 26.5% year on year to 2.165 billion won; per the source, the decline reflected reduced chip production by customers amid memory supply shortages and rising prices. The company expects royalty revenue to return to growth in 2027, with domestic fabless AI SoC customers scheduled to begin mass production of chips for robots, home appliances and IoT devices. Service revenue increased 66.8% to 565 million won, and the company swung to a net loss of 605 million won, which the source attributes to foreign exchange losses and valuation losses on financial assets. Chips&Media also said it plans to strengthen its position in the mobility market, expand into edge AI fields including robotics and drones, address demand for next-generation video codec standards APV and AV2, commercialize AI ISPs and further enhance its NPU IP.
IP licensingRoyalty revenueService revenueChips&Media, GoogleThe Elec
During its 3Q26 earnings call, SK hynix said it plans to maximize the potential of its existing 6F² architecture through process improvements and stable platform operations, while continuing to develop 4F² and 3D DRAM as potential next-generation options, with adoption tied to each technology's maturity and economic viability. According to News 1, SK hynix DRAM marketing head Park Joon-deok said advances in EUV lithography and process scaling offer further room to extend the 6F² platform, stressing that commercializing new cell architectures requires overcoming hurdles in yields, reliability, costs, product design and customer validation. By contrast, Micron has ruled out adopting 4F² DRAM currently, saying the technology is "not on the roadmap right now"; Micron President and Chief Technology and Product Officer Scott DeBoer said more than 20 years of research had failed to identify a sustainable scaling path, and that while technically feasible, the 4F² structure's process complexity and higher manufacturing costs limit its practical benefits. According to Chosun Biz, Samsung Electronics is developing a 4F² architecture based on vertical channel transistors (VCT), and Song Jae-hyuk, President and CTO of Samsung's Device Solutions (DS) division, confirmed the company's 4F² development efforts at SEDEX 2026 in Seoul on October 14. Separately, China's CXMT is pushing ahead with 4F² commercialization plans, aiming to launch its first 4F²-based server DDR5 RDIMM module by the end of 2026. SK hynix is also pursuing 4F² research: in a July blog post tied to VLSI 2026, it positioned 4F² vertical-gate (VG) DRAM as a way to extend scaling at sub-10nm nodes.
DRAM6F² DRAM4F² DRAMSK hynix, Micron and 4 totalTrendForce
At its Las Vegas event, Oracle announced an expanded partnership with Google and plans to bring Google's Tensor Processing Units (TPUs) to Oracle Cloud Infrastructure (OCI), with the chips available for selection within OCI beginning in 2027 and capacity increasing over the course of several years; Oracle says the deal will make it the first hyperscale cloud platform outside Google's own cloud services to offer the chips, though it did not mention the quantity of TPUs to be available next year or beyond. OCI president Mahesh Thiagarajan said different AI workloads have different compute needs and that bringing Google TPUs to OCI gives customers the flexibility to choose the right infrastructure for the performance, throughput, and economics of each AI workload. Alongside the TPU plan, Oracle announced on Tuesday the general availability of Nvidia Vera Rubin NVL72 systems and Nvidia Vera CPUs, plus plans to introduce HGX Rubin NVL8 systems without specifying when those would become available, as well as new ChatGPT integrations, Oracle AI Workspace, Oracle AI Security Mesh, and a deal with Snowflake. Oracle also posted record earnings in the quarter ending August 31, with revenue up 30 percent year over year.
Google Tensor Processing Units (TPUs)Nvidia Vera Rubin NVL72 systemsNvidia Vera CPUsOracle, Google and 3 totalThe RegisterPartnership/M&A
According to Trendforce, citing supply chain sources and local media, TSMC is weighing raising prices for its Chip on Wafer on Substrate (CoWoS) advanced packaging technology by as much as 20%; TSMC has yet to confirm the report. The reported cause is strained capacity amid AI demand and longer delivery times for chipmaking tools: equipment lead times have reportedly stretched from three to six months to as long as eight months, and TSMC has reportedly placed this year's equipment orders at existing prices instead of negotiating discounts. CoWoS combines logic dies and HBM stacks in a single package; Nvidia's Blackwell already pairs two large GPU dies with eight HBM3E stacks, while the upcoming Rubin and Rubin Ultra are expected to push integration further and increase pressure on packaging. Testing is another bottleneck: Blackwell reportedly takes three to four times longer to test than Hopper, and Rubin could need as much as seven times longer; server CPUs and custom ASICs also compete for advanced packaging capacity. Background: TSMC deputy co-COO Cliff Hou said that by July the company's expected equipment needs had reached 1.9 times its original estimate; earlier this month GlobalFoundries agreed to produce silicon interposers for TSMC's CoWoS in the U.S. under a five-year contract worth $2 billion, with production expected to ramp up in the first half of 2028; TSMC is reportedly also considering broader price increases for 2027, with advanced-process wafer prices expected to rise 5% to 10%, steepest for 2nm and 3nm-class node customers, and customers seeking capacity beyond original allocations facing premiums that could push some costs up by as much as 25%. Industry estimates cited by Trendforce put TSMC's monthly capacity at over 106,000 wafers in 2026, with a target of 227,000 wafers in 2027. If both packaging and wafer price increases materialize, AI hardware costs will likely climb further.
CoWoS先进封装先进制程晶圆硅中介层TSMC, Nvidia and 3 totalTom's HardwarePrice Movement
On October 21, during GTC Berlin, Nvidia announced several multi-billion-dollar deals with six major supply chain partners — Ibiden, Unimicron, Samsung Electro-Mechanics, SPIL, Amkor and KYEC — across substrates, advanced packaging, semiconductor testing and optical engines, to expand production capacity and reserve capacity for its AI accelerators; expanded supply is to be available from 2027 through 2028, with commitments and production roadmaps stretching through 2028. For substrates, Nvidia plans to secure 2.5x dedicated substrate capacity over the next three years: it earlier signed a deal to provide a multibillion-dollar capacity reservation advance to support Ibiden's Ono Plant in Japan (targeting 3x the plant's current capacity); the Samsung Electro-Mechanics deal will support facility upgrades and new plants in Busan and Sejong, with Nvidia projected to account for a significant portion of its output by 2028; a capacity reservation agreement with Unimicron supports its substrate expansion in Taiwan, expected to start providing capacity by Q2 2027 and reach full capacity by mid-2028. For co-packaged optics, Nvidia signed with SPIL to expand optical engine production capacity 15x (1,400%) by mid-2027, with plans to double again by the end of 2028. With Amkor, Nvidia targets a more-than-300% increase in interposer wafer capacity by the end of 2028 through advanced packaging expansion in South Korea; Amkor confirmed the deal is worth $1.3 billion, bringing Nvidia's total investment across Amkor's Arizona and South Korea facilities to $3 billion. For testing, on October 13 Nvidia signed a deal to pay KYEC $1.1 billion to reserve testing capacity at KYEC's new $1.4 billion U.S. facility (high-volume production slated to begin in April 2027; Singapore high-volume production expected to begin February 2027), with testing capacity expected to double from calendar 2026 to 2027; KYEC currently handles nearly all of Nvidia's chip testing. Per its August 2026 disclosures, Nvidia had accumulated $279 billion in outstanding supply and manufacturing-capacity commitments by July 2026. All expansion figures are announced plans and targets, not yet realized.
substratesadvanced packaginginterposer wafersNvidia, Ibiden and 7 totalTom's HardwareCapacity Change
Anthropic's IPO filing reveals an infrastructure strategy extending far beyond conventional cloud procurement: the Claude developer has locked in hundreds of billions of dollars of compute capacity across Google, Amazon, Microsoft, Broadcom, and a growing roster of GPU infrastructure providers, spanning TPUs, GPUs, and dedicated data centers. This is a capacity commitment arrangement disclosed in the IPO filing; the source does not state the cause.
AWS has launched the open-source TorchNeuron tool, allowing developers to port PyTorch artificial intelligence (AI) applications to its custom Trainium chips without rewriting code. Google has followed with TorchTPU, while AMD and Intel are integrating AI software optimizations, as chipmakers challenge Nvidia's market advantage built on the CUDA ecosystem.
TrainiumTorchNeuronTorchTPUAWS, Google and 5 totalDigiTimes Asia
Per Tom's Hardware on 26 October 2026, Micron outlined its next-generation DRAM technology plans: the company intends to introduce wafer bonding with its upcoming 1ε DRAM process technology and adopt High-NA EUV lithography (together with new materials) for the subsequent ζÅ (1st generation sub-10nm-class DRAM node) and ηÅ (2nd generation sub-10nm-class DRAM node) generations; it has not disclosed how it will implement wafer bonding or what improvements it expects. Micron's current 1γ DRAM process is already in high-volume manufacturing, while its successor 1δ is scheduled to enter volume production in the second half of 2027, promising a mid-20% increase in bit density and optimized for future AI memory products including HBM5, vHBM, and vEIM. Micron is also developing 3D DRAM (generations 3D1 and 3D2 on its roadmap, with architectures and launch schedules undisclosed) as well as vertical high-bandwidth memory (vHBM), vertical edge inference memory (vEIM), and various custom HBM (cHBM) implementations; the 1st generation vEIM targets 2 TB/s bandwidth at <1pJ/bit energy, in line with what HBM4 currently offers (at 8 GT/s over a 2,048-bit interface). The company has not disclosed when vHBM, vEIM, or cHBM will enter commercial production. Micron president and chief technology and products officer Scott DeBoer said 'DRAM is nearing atomic limits at this point,' adding that the company has confidence in several more planar nodes and will introduce 3D DRAM only at the optimal time from a cost and performance point of view. All items are plans/under development, not achieved results.
Intel CEO Lip-Bu Tan has reportedly discussed potential areas of cooperation with AMD CEO Lisa Su, but Tan did not publicly detail the reported areas of potential cooperation during his October 24 fireside chat with Chinese American Semiconductor Professional Association (CASPA) President Jimmy Cheng, and neither company has announced a new agreement arising from the discussions. In the chat, Tan outlined plans to rebuild Intel's CPU business, develop chips tailored to specific customer workloads, and grow ASICs, co-packaged optics (CPO), physical AI and advanced packaging as potential growth businesses, with two or three of these areas eventually contributing around 10% of Intel's revenue each. He said the 18A process had reached volume production, 14A development was progressing strongly, PDK version 0.5 was released, version 0.9 was coming next, followed by version 1.0 for volume production in early 2027. In January, two prospective customers were evaluating 14A test chips, with firm supplier decisions expected during the second half of 2026 and the first half of 2027, though Intel did not identify those customers or disclose order sizes. The companies already cooperate: in October 2024 Intel and AMD established the x86 Ecosystem Advisory Group, and last week it emerged that AMD was integrating its ZenDNN optimizations into Intel's open-source oneDNN library.
Former Intel CEO Pat Gelsinger, who became a partner at investor Playground Global last year, is betting on Nagare Labs, a startup founded by Georgia Institute of Technology professors Suman Datta and Shimeng Yu, which is developing a new memory technology called Z2RAM based on oxide semiconductors. Z2RAM aims to combine SRAM-like speed, density much closer to DRAM, and NAND-like manufacturing, with a promised bit density upwards of 5x that of SRAM in its first incarnation (a 64MB SRAM tile corresponding to 320MB of Z2RAM capacity), designed for integration directly onto compute logic using 3D hybrid bonding. The company has closed its first seed funding round and now has $5 million to further development; the technology is still at the lab-prototype stage, and Nagare is looking for an R&D fab partner, with the goal of sampling working Z2RAM memory tiles within the next four years and production shipments within the next decade. Challenges include the lack of an open standard for 3D bonding integration (Nagare may have to design an interface itself) and reliability concerns with oxide semiconductors (atomic vacancies and single- or few-electron effects shifting transistor threshold voltage).
Z2RAMSRAMDRAMNagare Labs, Intel and 7 totalThe RegisterPartnership/M&A
Google's Project Suncatcher is testing AI hardware in space; in that environment, radiation, cooling, power, and hardware lifetime determine the economics of computing. The article is titled "In Orbit, Useful Life Becomes a Performance Metric," and the source states no further details beyond these factors, with no specific part numbers, quantities, or dates given.
SK hynix is scheduled to report 3Q26 results on October 28. Per Newsis, market consensus projects 3Q26 consolidated revenue at KRW 98.23 trillion and operating profit at KRW 76.96 trillion, up 301.76% and 576.11% year over year; per Chosun Biz, that implies a 78.4% operating margin, with fourth-quarter operating profit projected to climb further to KRW 87.27 trillion. Brokerage estimates are widely split: SK Securities projects third-quarter operating profit of KRW 79 trillion, while DS Investment & Securities and Meritz Securities forecast KRW 70.1 trillion and KRW 80.1 trillion respectively—a gap of KRW 10 trillion. Per Chosun Biz citing industry sources, amid delays in NVIDIA's Rubin rollout and longer-than-expected performance tuning for mass-produced chips, SK hynix's HBM4 shipments may have fallen short of expectations for a second consecutive quarter in 3Q26; per Money Today citing JPMorgan, HBM4 ASPs are estimated to rise 121% by 2027 compared with 2025 levels. Per DealSite citing Hana Securities, after a 30% jump in DRAM ASPs and a mid-50% surge in NAND ASPs in 2Q26, third-quarter DRAM ASPs are expected to rise another 21% QoQ, potentially lifting the DRAM segment's operating margin to 83%, with NAND ASPs projected to gain 17% sequentially. On LTAs: Samsung reportedly plans to allocate 60–70% of its memory production capacity to long-term contracts; SK hynix disclosed at its July earnings call that it had signed multi-year deals with around 10 customers, including major clients; per Business Post citing KeyBanc, HP and Dell have extended their memory supply agreements with Micron through 2031, while Alphabet is seeking contracts with memory suppliers lasting until 2035. Separately, SK hynix has decided to shelve the IPO of its U.S. subsidiary Solidigm, with no concrete funding plan disclosed; per Hankook Ilbo, potential options range from internal cash and borrowing to joint ventures and customer-backed financing tied to long-term supply agreements.
HBM4DRAMNANDSK hynix, Samsung and 5 totalTrendForcePrice Movement
Victor Lopez, Co-Founder and CTO of RaiderChip with over 20 years of experience in FPGA and ASIC design, gives an interview about the company. RaiderChip is a European fabless semiconductor company founded in 2024, developing a proprietary NPU architecture to bring Generative AI directly to edge devices; its business model combines chip development with licensing the NPU architecture as IP for integration into third-party SoCs. The technology targets Transformer inference, with strongest application areas in robotics, automotive, and industrial automation. The company is currently moving towards the tape-out of Kairós, its first-generation chip (a plan in progress, not yet completed); in the meantime it offers demonstrations on an FPGA-based NPU prototype that supports more than 50 models and is available for evaluation under a non-disclosure agreement. The company also presented a robotics demonstration: robots and their physics are simulated in MuJoCo, Google DeepMind's physics simulator, while the intelligence runs on real hardware, the Kairós FPGA-based NPU prototype; a speech recognition model transcribes instructions, a four-billion-parameter reasoning model interprets objectives and plans movements as a timed sequence of velocities, and all ten models, including speech recognition, reasoning, and robotic control policies, execute concurrently on a single NPU, locally and in real time, without any cloud connection. Lopez also cites customer concerns about technological sovereignty and strategic dependence on a small number of international suppliers of advanced technologies, noting recent geopolitical tensions and export restrictions on advanced hardware.
According to Tom's Hardware, published 25 October 2026, AMD Director of Client Product Management Travis Kirsch told the Japanese publication MyNavi Tech+ that AMD CEO Lisa Su was one of the proponents of bringing back the Ryzen 7 5800X3D processor, which first debuted in April 2022. The relaunch was not a simple re-release: the company had to do extensive re-engineering and update its manufacturing process with TSMC to bring it back. The relaunch of the Ryzen 7 5800X3D coincided with the memory chip shortage, with the world suffering from extremely high DDR5 memory prices (DDR5 finally arrived in the middle of 2026), but Kirsch said 'this was planned before changes in the memory market occurred, not as a countermeasure to DDR5 shortages,' calling it 'the final gift to local users who have used our AM4 for nearly a decade, offering systems that use DDR4 the last change to upgrade their PCs.' Kirsch also said AMD is mostly focused on the premium, high-performance gaming market (AMD closed in on Intel at 48.4% CPU share in the October Steam Survey), while the affordable CPU market is no longer as big as it used to be as laptops have taken over that segment.