Micron plans to use wafer bonding and High-NA EUV for next-gen DRAM

What happened

Per Tom's Hardware on 26 October 2026, Micron outlined its next-generation DRAM technology plans: the company intends to introduce wafer bonding with its upcoming 1ε DRAM process technology and adopt High-NA EUV lithography (together with new materials) for the subsequent ζÅ (1st generation sub-10nm-class DRAM node) and ηÅ (2nd generation sub-10nm-class DRAM node) generations; it has not disclosed how it will implement wafer bonding or what improvements it expects. Micron's current 1γ DRAM process is already in high-volume manufacturing, while its successor 1δ is scheduled to enter volume production in the second half of 2027, promising a mid-20% increase in bit density and optimized for future AI memory products including HBM5, vHBM, and vEIM. Micron is also developing 3D DRAM (generations 3D1 and 3D2 on its roadmap, with architectures and launch schedules undisclosed) as well as vertical high-bandwidth memory (vHBM), vertical edge inference memory (vEIM), and various custom HBM (cHBM) implementations; the 1st generation vEIM targets 2 TB/s bandwidth at <1pJ/bit energy, in line with what HBM4 currently offers (at 8 GT/s over a 2,048-bit interface). The company has not disclosed when vHBM, vEIM, or cHBM will enter commercial production. Micron president and chief technology and products officer Scott DeBoer said 'DRAM is nearing atomic limits at this point,' adding that the company has confidence in several more planar nodes and will introduce 3D DRAM only at the optimal time from a cost and performance point of view. All items are plans/under development, not achieved results.

Impact and signal

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Source and time

Source: Tom's Hardware · 10/26/2026 · View original source