Cadence Design Systems used its third-quarter earnings call to argue that demand for chip design tools is no longer tied only to the AI hardware buildout, pointing to analog and memory chipmakers, system companies, and new entrants such as space and finance firms designing their own silicon. On the October 26 call, analysts pressed two questions that will shape the coming year: how much growth comes from agentic AI rather than hardware, and whether Cadence can match the long-term targets rival Synopsys set a month earlier.
Cadence Design Systems said revenue for the three months ended September 30, 2026 rose 22% from a year earlier, with the results announced on October 26. The company said AI-driven design work is showing up in both revenue and backlog, with backlog at a record level, and it raised its 2026 outlook (a forecast/guidance, not an achieved result). The company also said the cost of buying growth is hurting profitability, while operating income barely moved.
chip design toolsCadence Design SystemsDigiTimes Asia
According to industry sources on Oct. 26, LB Semicon plans to expand its back-end processing capacity for power management integrated circuits (PMICs) supplied to Qualcomm: it will increase its 200mm wafer-based non-display driver IC (non-DDI) packaging capacity at its Pyeongtaek headquarters plant from 26,000 to 36,000 wafers per month and its 300mm capacity from 3,000 to 5,000 wafers per month, both by 2028, with total investment of approximately 30 billion won. The source-stated cause is meeting Qualcomm's demand and preparing for a potential transition to 300mm processes and higher production volumes; the expansion is also a contractual requirement. LB Semicon provides turnkey services covering bumping, testing and back-end processing for Qualcomm's PMICs used in AI data centers and automobiles. The partnership began in the second half of 2024; after passing Qualcomm's technical review, QMS audit and reliability verification, LB Semicon received mass production approval in August, began mass production in early August and shipped its first products later that month, using copper pillar bump (CPB) and wafer-level packaging (WLP) technologies. The company said it signed a 10-year master supply agreement (MSA) with Qualcomm; per a securities registration statement filed in May, the MSA took effect on Feb. 1 this year, is valid for 10 years with automatic renewals every two years, Qualcomm issues purchase orders (POs), and LB Semicon must continuously maintain reserve capacity equal to 10% of Qualcomm's six-month demand forecasts provided monthly. Once the expansion is completed, annual revenue from the Qualcomm PMIC lines is projected to rise from a current maximum of approximately 30 billion won to around 50 billion won in 2028, equivalent to 10.4% of last year's annual revenue, with revenue expected to increase by approximately 9.5 billion won beginning in the second half of next year. The investment will be funded with 30 billion won allocated to capital expenditures from the 34.26 billion won raised through a rights offering in August, of which 24.8 billion won will go to bumping processes and 5.2 billion won to back-end processes; 15 pieces of equipment, including electroplating, lithography and sputtering systems, will be delivered in stages from the fourth quarter of this year through the fourth quarter of next year. LB Semicon reported consolidated revenue of 279.168 billion won and operating profit of 20.752 billion won in the first half of this year, with DDI products accounting for more than 70% of revenue.
According to industry sources on Oct. 26, South Korea's Ministry of Trade, Industry and Resources (MOTIR) is planning an OLED research and development project for fighter jet cockpits with LG Display and Hanwha Systems. OLED displays for fighter jets are expected to adopt multi-stack tandem structures with more emissive layers than smartphone displays: fighter jets have greater power supply capacity than smartphones, allowing additional emissive layers to improve brightness and lifespan, while adding emissive layers also increases the required driving voltage. Large cockpit displays in South Korea's KF-21 fighter jet and the U.S. F-15 series currently use liquid crystal displays (LCDs). Key development priorities include suppressing lateral current leakage through the charge generation layers (CGLs) between emissive layers, which could make adjacent pixels that should remain off emit faint light and distort colors during nighttime low-brightness operation; improving red-emitting materials whose long-wavelength emissions can be amplified by night vision goggles and interfere with pilots' observation; optical technologies that narrow the direction of light emission, such as microcavities, distributed Bragg reflectors (DBRs) and metalenses, as alternatives to the viewing-angle restriction films LCDs use, which cause light loss, increasing power consumption and heat generation; and overcoming OLED brightness degradation at low temperatures such as around minus 40 degrees Celsius, while withstanding vibration and shock with redundancy. An industry official said that to apply OLED technology to actual military equipment, manufacturers must secure improvements in lifespan through multi-stack tandem structures alongside advances in emissive materials and optical design.
As advanced packaging shifts toward large-size glass substrates, Cheng Mei Materials Technology is developing materials to address warpage, heat resistance, and drilling challenges. Its cutting and grinding tapes have entered customer validation and small-volume testing, while its anti-warpage film and heat-resistant tape remain in development.
advanced packaging glass substratescutting and grinding tapesanti-warpage filmCheng Mei Materials TechnologyDigiTimes Asia
Apple’s first foldable smartphone, the iPhone Duo, is reportedly facing quality concerns over display damage near the hinge. According to MacRumors on October 26, Apple acknowledged an issue affecting the inner displays of a small number of iPhone Duo units, but did not disclose the cause of the cracking or whether a fix is planned; affected customers have been able to obtain in-store replacements, though limited inventory has left some waiting. According to ZDNet (citing MacRumors), persistent hinge problems during development prompted supplier changes: U.S.-based Amphenol was initially the primary hinge supplier with Taiwan’s Shin Zu Shing as secondary; Shin Zu Shing took over after Amphenol’s production yields fell well below expectations, but reportedly also struggled, having to select units meeting Apple’s quality standards as “golden samples,” and these difficulties delayed iPhone Duo production. Reuters adds that iFixit, via a 3D hinge simulation based on teardown footage, patents, and CT scans, suggested a possible cause: a central support bar may fail to retract properly during folding, placing pressure on the inner display. According to NewsPim, Apple has reportedly asked Foxconn and component suppliers to raise the iPhone Duo shipment target for the next 12 months by 44%, from 9.7 million to 14 million units; industry sources suggest the increase reflects stronger-than-expected initial demand plus additional component stockpiling for potential assembly defects, and Foxconn’s final assembly yield was reportedly around 60% in September, with hinge-related defects potentially further increasing demand for replacement OLED panels. TrendForce notes early screen-failure reports could undermine consumer confidence, with the long-term impact largely depending on how widespread the issue is and how quickly Apple identifies the root cause and repairs or replaces affected units. Separately, per ZDNet, another potential supply constraint is T-glass, a high-end fiberglass yarn used in copper-clad laminates (CCLs) for PCBs, where Japan’s Nittobo holds a near-monopoly and is prioritizing shipments for AI chips made by companies such as NVIDIA, potentially adding pressure to Apple’s supply chain.
hingeinner OLED displayT-glassApple, Amphenol and 6 totalTrendForce
Related manufacturers
Apple, Amphenol, Shin Zu Shing, Foxconn, Nittobo, NVIDIA
According to ZDNet, Samsung and SK hynix are preparing to ship 8-Hi HBM4 for Rubin Ultra in 2Q27, departing from the original 12-Hi HBM4E plan; 8-Hi HBM4 was initially absent from NVIDIA's plans, but talks gained traction in 3Q26. The source cites thermal challenges and lower yields in 12-Hi stacks, potentially easing supply constraints. Although both Samsung and SK hynix have completed NVIDIA's qualification for 12-Hi HBM4, their 8-Hi products require separate certification; a source said NVIDIA is expected to deploy both 8-Hi HBM4 and 8-Hi HBM4E in Rubin Ultra-based NVL rack-scale systems depending on rack configuration. TrendForce says 8-Hi configurations use fewer DRAM dies, lowering cost per stack and GPU bill of materials, and given tight HBM supply, 8-Hi setups are expected to be a priority for evaluation by many GPU and ASIC vendors in 2027; ZDNet reports 12-Hi HBM4 remains mainstream in 2026, with 8-Hi adoption expected to rise sharply from mid-2027. Economy Tribune, citing Daishin Securities, suggests Anthropic's in-house AI chip could also feature 8-Hi HBM4, raising the prospect of Samsung supplying both foundry services and memory. Separately, per Wccftech, NVIDIA trimmed Vera Rubin's HBM4 bandwidth specifications: an archived September 1 version listed the Vera Rubin NVL72 system with 20.7 TB of HBM4 capacity and 1,580 TB/s bandwidth, the Vera Rubin Superchip at 576 GB and 44 TB/s, and each Rubin GPU at 288 GB and 22 TB/s; NVIDIA has since lowered per-GPU HBM4 bandwidth to 19.2 TB/s and NVLink 6 throughput from the originally advertised 3.6 TB/s to 3 TB/s, cuts of roughly 13% and 17% respectively, and up to 26% for HGX Rubin NVL8 systems, with changes dating back to September. IT Home notes NVIDIA revised the Vera CPU memory specification from a fixed 1.5 TB of LPDDR5X per chip to 'up to 1.5 TB', and that lowering bandwidth requirements could allow more HBM4 products to qualify for Rubin GPUs, potentially boosting overall production output.
HBM4HBM4ELPDDR5XNVIDIA, Samsung and 4 totalTrendForceCapacity Change
Intel is actively planning the "Raptor Lake Next" chips as an update to its Socket LGA-1700 desktop processors. These chips are essential for PC buyers who are limited to the decade-old DDR4 memory standard due to the high prices of DDR5 memory, especially since the current Core Ultra "Arrow Lake" processors do not support DDR4. Two "Raptor Lake Next" chips have appeared in shipping manifests, which usually indicate that the CPUs are being shipped as samples to customers or as part of a production run returning to Intel, suggesting a nearby launch. Four SKUs have been identified, labeled 99DLMV, 99DLMT, 99DLMW, and 99DLMX, but details exist on only two models: the 99DLMV is a 16-core design with 8 P-Cores and 8 E-Cores, a clock speed of 3.5 GHz, 30 MB of CPU cache, and a TDP of up to 125 W; the 99DLMT is a 20-core SKU with 8 P-Cores and 12 E-Cores, running at 2.1 GHz, with a CPU cache capacity of 33 MB, and a TDP of 65 W. These leaked models align with previous rumors, such as the one suggesting that Intel plans to replace the Core i5-14600K with a new "Raptor Lake Next" chip featuring 8 P-Cores and 8 E-Cores, so the 99DLMV SKU might be the one previously speculated about.
According to a leaked PassMark benchmark spotted by VideoCardz, the upcoming Intel Nova Lake-S CPU family, headed by a 28-core Core Ultra 9 CPU, appears in the database as "Nova Lake Client Platform" with motherboard model "NVL-S Embedded CRB 1 Fab2 Board." In the single-threaded benchmark, the eight-core NVL-S scores up to 5,085 points and the 24-core variant tops out at 5,210 points; in the multithreaded test, the 28-core CPU (ostensibly the Core Ultra 9 4970K BFC) scores as high as 61,509 points, while the eight-core variant (likely a Core Ultra 3 or 5) scores 23,478 points. If the PassMark scores are accurate, the Core Ultra 9 4970K BFC reaches around 85% of the multicore performance of an AMD Ryzen 9 9950X3D, and beats the Intel Core Ultra 9 285K on single-threaded performance while missing out on matching that outgoing Intel chip by 5,721 points or around 8.5%. This is a leaked benchmark, not official data.
28-core Intel Nova Lake-S CPUeight-core NVL-S CPU24-core NVL-S CPUIntelTechPowerUp
According to supply chain sources cited by Commercial Times, as increasingly large AI accelerators strain advanced packaging capacity, TSMC's CoWoS supply remains tight, and TSMC is reportedly weighing price hikes of up to 20%, with some packaging lead times already stretching; Commercial Times reports that foundries and OSAT providers are considering another round of CoWoS price increases of 10%–20%. The stated backdrop is that advanced packaging demand is expanding beyond AI GPUs to server CPUs and custom ASICs, adding to a growing backlog of unfilled orders; longer AI chip testing times are an additional bottleneck, with Seoul Economic Daily citing Nomura Securities that NVIDIA Blackwell's final testing takes an estimated four times as long as Hopper's, while Rubin could require seven times as long. On equipment, Commercial Times reports equipment lead times have lengthened to six to eight months, up from three to six months, as customers prioritize securing deliveries over negotiating prices; TSMC, which typically negotiates price cuts or additional features at no extra cost, reportedly placed equipment orders at existing prices this year without seeking discounts or upgrades. Separately, according to Liberty Times, TSMC has finalized plans to raise wafer-out prices by 3%–6% starting January 2027, depending on the process node, with advanced nodes such as 2nm and 3nm seeing the steepest increases. On capacity, analysts cited by Commercial Times estimate monthly CoWoS capacity will exceed 130,000 wafers in 2026 and target 200,000 in 2027; Goldman Sachs projects TSMC's CoWoS capacity to reach 1.275 million wafers in 2026 (roughly 106,000 per month), before surging 114% YoY to 2.73 million in 2027 (227,500 monthly), and climbing another 27% to 3.48 million wafers in 2028 (nearly 290,000 per month). At its latest earnings call, Chairman and CEO C.C. Wei highlighted strong yields for its 5x reticle-size packaging, already in mass production, while confirming development of 9x and 14x solutions; the company is also advancing CoPoS to support larger packages at lower costs, with Commercial Times pointing to a 2028 timeline for 14x packaging. The price increases remain reported or planned and the article does not state they have been formally implemented.
Accellera Systems Initiative has approved Functional Safety Language Standard 1.0 (FSL 1.0) for release, announced October 21, and the standard is available for download. The standard establishes a common language and data model for capturing, exchanging, and integrating functional safety information throughout electronic systems development, focusing on failure modes, effects, and diagnostic analysis (FMEDA). It supports hierarchical FMEDAs, both assumption-based and design-mapped approaches, refining estimated diagnostic coverage using verification and fault-injection results, Tcl-based syntax for machine processing, and calculation and reporting of safety-related failure rates and metrics associated with ISO 26262 and IEC 61508. It targets reliable movement of safety information across tools, engineering teams, and companies, from IP through integrated circuits to systems. The source states that adopting FSL alone does not demonstrate compliance or certify a product, existing standards retain their requirements, and the standard's value will depend on adoption by tool vendors, suppliers, and customers.
Functional Safety Language Standard 1.0 (FSL 1.0)Accellera Systems InitiativeSemiWiki
Reported on 2026-10-27: two developments highlight growing momentum in Micro LED optical interconnect. U.S. smart glasses and optical waveguide developer Vuzix unveiled its Vuzix Causeway optical interconnect evaluation platform, based on its proprietary diffractive waveguide technology, at the 2026 OCP Global Summit (held October 12–15, 2026 in San Jose, California), targeting AI data center, semiconductor, and photonics applications; the current evaluation platform supports 19,200 parallel optical paths over an optical path length of approximately 30mm, and once light sources, detectors, and system integration are completed, the technology is expected to support aggregate bandwidth in the multi-terabit range (expected, not yet achieved), with a waveguide architecture compatible with Micro LED and VCSEL light sources; Vuzix is making evaluation units available to qualified industry partners and shipped its first Causeway waveguide bridge samples to selected customers in August. On the funding side: on October 14, Beijing-based Xinghuo Chenguang Technology announced completion of its first funding round, led by Sequoia China with San'an Optoelectronics participating as a follow-on investor and Yunxiu Capital as exclusive financial advisor for subsequent funding rounds; the amount raised was not disclosed. Xinghuo Chenguang develops Micro LED-based optical interconnect chips, targeting high-speed, low-power data exchange between chips and between computing and memory in AI and high-performance computing systems. On technology progress: on September 28, Xinghuo Chenguang, Yuanxu Optoelectronics, and Tsinghua University announced a milestone in Micro LED optical interconnect chip R&D joint testing by Tsinghua University and Xinghuo Chenguang showed a Micro LED chip sample achieved a -3 dB bandwidth of 3.5 GHz at a current density of 500 A/cm², demonstrating high-speed response at the 3 GHz level. In the next phase the three parties will focus on device consistency, array integration, and packaging interconnects, and conduct link-level testing to validate communication performance.
Micro LED optical interconnect chipoptical interconnect evaluation platformdiffractive waveguideVuzix, San'an Optoelectronics and 6 totalTrendForcePartnership/M&A
According to a report dated 2026-10-27, Shanghai-based Jiachi Power Technology, located in Shanghai's fourth-generation semiconductor industry cluster, has completed the first phase of wafer fabrication and validation for its vertical gallium oxide MOSFET chips. Through device-structure innovations and in-house process development, the company describes the result as the world's first enhancement-mode vertical gallium oxide MOSFET with on-state current exceeding 1 A and breakdown voltage above 900 V. Measured results showed a threshold voltage of 3.9 V enabling stable enhancement-mode operation, an on-state current of 1.2 A, and a specific on-resistance of 33 mΩ·cm². Designed for a 750 V operating class, the device demonstrated a measured breakdown voltage exceeding 900 V with leakage current below 3 μA, which the source says approaches mature commercial silicon and silicon carbide power devices. Based on the company's review of publicly available research and industry results, this is the first reported vertical gallium oxide MOSFET with on-state current above 1 A. Stable and controllable p-type doping had long been a major challenge, and prior public literature had not documented vertical gallium oxide MOSFETs with on-state currents exceeding 1 A. The technical team said the results validate the feasibility of its original device architecture and in-house self-aligned ion implantation approach, marking an important step from laboratory validation toward commercial engineering. Going forward, the company plans to further optimize device structures, process parameters, and epitaxial material integration, and to advance chip development, sample delivery for customer evaluation, and production-ready process establishment.
vertical gallium oxide MOSFETJiachi Power TechnologyTrendForce
Nvidia has effectively sent JEDEC back to the drawing board with its HBM standard: Nvidia revolted against HBM memory controller functionality being in its GPU chip and, in its NVHBM custom HBM standard, moved it to the HBM base die unit, freeing up space for more GPU cores; the change is part of its August NVLInk Fusion announcement. Nvidia claims (a vendor claim, not a verified achieved result) that, compared with standard HBM4E, NVHBM delivers up to 30 percent greater memory bandwidth, 15 percent lower HBM power consumption, and frees up to 25 percent more area on its GPU compute die; this is specific to Nvidia and is not an industry standard. According to reported Morgan Stanley data, Nvidia will be responsible for purchasing 37 percent of the global HBM supply in 2027, so the three HBM suppliers — Samsung, SK Hynix and Micron — are supporting NVHBM and even let Nvidia dictate that they must use TSMC's 3nm foundry process; Reuters reported Samsung will accede to this request, but per Seoul Economic Daily, Samsung would still build JEDEC standard HBM in-house for other customers. Amazon's Annapurna Labs is also supporting NVHBM as an Nvidia NVlink partner. JEDEC has not issued any public comment about NVHBM; when JEDEC announced the HBM4 standard in April last year, the HBM subcommittee chair was Barry Wagner, Director of Technical Marketing at Nvidia. Beyond the stated reason of freeing GPU-core space and moving the memory controller, the source does not state another cause.
HBMHBM4EHBM4Nvidia, Samsung and 5 totalBlocks & Files
This is a background technical explainer about TSMC's CoWoS-S (Chip-on-Wafer-on-Substrate with a silicon interposer) 2.5D integration platform, which places large logic dies or chiplets beside multiple high-bandwidth-memory stacks and connects them through dense wiring in a silicon interposer, producing multi-terabyte-per-second memory interfaces. TSMC reports the platform has been in production since 2012 and supports silicon interposers reaching approximately 3.3 times reticle size; its fifth-generation implementation demonstrated an interposer of about 2,500 square millimeters capable of accommodating multiple logic chips and eight HBM stacks. The article also describes power-integrity features (embedded deep-trench capacitors), thermal and mechanical engineering challenges, and notes that packaging capacity determines how quickly cloud providers can deploy new computing clusters. The source does not state the cause of any event, as this is background technology analysis with no price movement, capacity change, or policy event reported.
TSMC CoWoS-S (Chip-on-Wafer-on-Substrate with silicon interposer)2.5D integration platformsilicon interposerTSMCSemiWiki
Rambus and ChipAgents have announced a multi-faceted strategic agreement to accelerate chip design with agentic AI. As part of the agreement, Rambus is adopting the ChipAgents platform companywide, including deployment across its chip and silicon IP design and verification workflows to accelerate the pace of development. The two US companies will also collaborate to leverage Rambus' semiconductor expertise and ChipAgents' agentic AI platform and agentic workflows to enable greater speed and Quality of Results (QoR) in Rambus customers' chip design process across their preferred design environments. In addition, Rambus has become a strategic investor in ChipAgents. These points come from a press release; the announcement's actual implementation outcomes are not stated in the source.
SEMICON West 2026 was held October 13 to 15 at the Moscone Center in San Francisco. The article states the opening toast marked an industry that has already crossed $1 trillion in annual revenue, almost four years ahead of earlier projections. According to WSTS (World Semiconductor Trade Statistics), first-half 2026 sales were $702 billion, double a year earlier, and its August update points to roughly $1.66 trillion for the full year (a forecast), with memory up about 300% (forecast). SEMI expected more than 35,000 attendees over the three days on a sold-out floor of over 1,500 booths, with an exhibitor count of more than 700 companies and organizations. Topics included AI scaling, heterogeneous integration, advanced manufacturing, supply-chain resilience, advanced packaging and the economics of agentic AI. The next SEMICON West opens in Phoenix in March 2027; PDF Solutions held its 2026 CONNECT Conference on October 15–16 in San Francisco. The full-year sales figure is a WSTS forecast, not an achieved result.
Intel CEO Lip-Bu Tan has reportedly discussed potential areas of cooperation with AMD CEO Lisa Su, but Tan did not publicly detail the reported areas of potential cooperation during his October 24 fireside chat with Chinese American Semiconductor Professional Association (CASPA) President Jimmy Cheng, and neither company has announced a new agreement arising from the discussions. In the chat, Tan outlined plans to rebuild Intel's CPU business, develop chips tailored to specific customer workloads, and grow ASICs, co-packaged optics (CPO), physical AI and advanced packaging as potential growth businesses, with two or three of these areas eventually contributing around 10% of Intel's revenue each. He said the 18A process had reached volume production, 14A development was progressing strongly, PDK version 0.5 was released, version 0.9 was coming next, followed by version 1.0 for volume production in early 2027. In January, two prospective customers were evaluating 14A test chips, with firm supplier decisions expected during the second half of 2026 and the first half of 2027, though Intel did not identify those customers or disclose order sizes. The companies already cooperate: in October 2024 Intel and AMD established the x86 Ecosystem Advisory Group, and last week it emerged that AMD was integrating its ZenDNN optimizations into Intel's open-source oneDNN library.
Former Intel CEO Pat Gelsinger, who became a partner at investor Playground Global last year, is betting on Nagare Labs, a startup founded by Georgia Institute of Technology professors Suman Datta and Shimeng Yu, which is developing a new memory technology called Z2RAM based on oxide semiconductors. Z2RAM aims to combine SRAM-like speed, density much closer to DRAM, and NAND-like manufacturing, with a promised bit density upwards of 5x that of SRAM in its first incarnation (a 64MB SRAM tile corresponding to 320MB of Z2RAM capacity), designed for integration directly onto compute logic using 3D hybrid bonding. The company has closed its first seed funding round and now has $5 million to further development; the technology is still at the lab-prototype stage, and Nagare is looking for an R&D fab partner, with the goal of sampling working Z2RAM memory tiles within the next four years and production shipments within the next decade. Challenges include the lack of an open standard for 3D bonding integration (Nagare may have to design an interface itself) and reliability concerns with oxide semiconductors (atomic vacancies and single- or few-electron effects shifting transistor threshold voltage).
Z2RAMSRAMDRAMNagare Labs, Intel and 7 totalThe RegisterPartnership/M&A
KOA Speer Electronics introduced a new family of heat shock resistors featuring a metal glaze resistance film to provide improved high heat and weather resistance. The RK73B-AT resistors also feature a thicker bottom electrode to suppress cracking and delamination caused by thermal shock; the company highlights that this enhanced solder joint reliability applies to both high-strength solders and SAC (Sn-Ag-Cu) solders. The company states the resistors are capable of withstanding two to three times the number of thermal cycles compared to standard chip resistors, and, in terms of improved temperature cycle resistance, their design is for 1,000 to 2,000 cycles to increase product life expectancy. The lead time for the resistors is eight weeks, with samples available upon request. RK73B-AT specifications: power rating 0.1W ~ 0.25W; resistance range 1 ~ 22MΩ; tolerance ±2%, ±5%; TCR ±200ppm/°C ~ ±400ppm/°C; sizes 0402 – 1206. Note: its heat shock resistors use a part number designation of -AT.