[News] Vuzix Enters Optical Interconnect, San’an Backs Micro LED Startup, Hint at AI Transmission Market

What happened

Reported on 2026-10-27: two developments highlight growing momentum in Micro LED optical interconnect. U.S. smart glasses and optical waveguide developer Vuzix unveiled its Vuzix Causeway optical interconnect evaluation platform, based on its proprietary diffractive waveguide technology, at the 2026 OCP Global Summit (held October 12–15, 2026 in San Jose, California), targeting AI data center, semiconductor, and photonics applications; the current evaluation platform supports 19,200 parallel optical paths over an optical path length of approximately 30mm, and once light sources, detectors, and system integration are completed, the technology is expected to support aggregate bandwidth in the multi-terabit range (expected, not yet achieved), with a waveguide architecture compatible with Micro LED and VCSEL light sources; Vuzix is making evaluation units available to qualified industry partners and shipped its first Causeway waveguide bridge samples to selected customers in August. On the funding side: on October 14, Beijing-based Xinghuo Chenguang Technology announced completion of its first funding round, led by Sequoia China with San'an Optoelectronics participating as a follow-on investor and Yunxiu Capital as exclusive financial advisor for subsequent funding rounds; the amount raised was not disclosed. Xinghuo Chenguang develops Micro LED-based optical interconnect chips, targeting high-speed, low-power data exchange between chips and between computing and memory in AI and high-performance computing systems. On technology progress: on September 28, Xinghuo Chenguang, Yuanxu Optoelectronics, and Tsinghua University announced a milestone in Micro LED optical interconnect chip R&D joint testing by Tsinghua University and Xinghuo Chenguang showed a Micro LED chip sample achieved a -3 dB bandwidth of 3.5 GHz at a current density of 500 A/cm², demonstrating high-speed response at the 3 GHz level. In the next phase the three parties will focus on device consistency, array integration, and packaging interconnects, and conduct link-level testing to validate communication performance.

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Source: TrendForce · 10/26/2026 · View original source