TrendForce published a forecast on October 27, 2026: the PMIC market is set to reach $44.7B in 2026, growing 8.4% YoY. The source attributes the growth to AI, automotive electrification, and data centers; it also states that as AI chip power consumption passes 1kW, PMICs are becoming the core of intelligent power management, focused on IVR/PIVR, 800VDC, and digital telemetry, with global leaders and Asian suppliers speeding up work on full-stack power platforms. The figure is a forecast, not an achieved result.
PMIC（高压PMIC，聚焦IVR/PIVR、800VDC与数字遥测）TrendForce Official (Market Data)
Anglia Components, one of Europe's longest-established independent authorised distributors of electronic components, has signed a Pan-European franchise agreement with NOVOSENSE Microelectronics, the Chinese manufacturer of highly robust and reliable analog and mixed signal ICs. Anglia's Marketing Director John Bowman explained that the agreement is part of Anglia's strategy to offer customers alternative solutions to the big US analog companies, which are causing difficulties—especially to SME customers—with repeated price increases and restrictions to their supply chain; he said Anglia has rigorously evaluated NOVOSENSE and will add its ranges of ADCs, LED drivers, amplifiers, sensors, interface, motor driver, and gate driver ICs to its portfolio. Anna Wang, Head of NOVOSENSE EMEA, added that Anglia's long experience in the UK and Ireland and its well-established pan-European e-commerce platform Anglia Live will enable customers in the UK and Europe to experience the value of NOVOSENSE's products in their new design projects. The article notes NOVOSENSE's sensor, signal chain, and power management products are widely used in the automotive, industrial, information, communication and consumer electronics markets. The agreement signing itself is an announced event; no effective date is stated in the source.
ADCsLED driversamplifiersNOVOSENSE Microelectronics, Anglia ComponentsEE JournalPartnership/M&A
S2C showcased FPGA prototyping and AI-assisted debugging at the sixth RISC-V Summit China (October 18–20, Shenzhen Convention and Exhibition Center). In its booth demonstration, an Andes Technology AX66-based RISC-V configuration ran Linux KVM on S2C's Prodigy S8-100 FPGA prototyping system, using 55% of the resources available on a single AMD Versal Premium VP1902 FPGA; the source states this demonstration and utilization figure should not be read as measurements of final silicon performance or application throughput. S2C also demonstrated RCF Agent using RTL from the open-source XiangShan RISC-V processor; the agent starts compilation, gathers error messages, and generates an initial analysis, but the demonstration concerned initial analysis only and did not establish that the agent independently resolves every error or replaces engineering review. In the summit's chip design and verification forum, S2C presented "LLM-based RISC-V Virtual Platform & Debug Flow," a proposed workflow combining a virtual platform modeling the processor, memory, buses, interrupt controller, and common peripherals with an LLM-assisted layer that interprets captured debug information; the platform can boot firmware, bootloaders, and operating systems and supports breakpoints, watchpoints, state inspection, and execution tracing. The source does not state the cause (no cause-related event).
RISC-V processorsS2C, Andes Technology and 3 totalSemiWiki
Intel recently announced its D-series "Crescent Island" inference graphics cards, based on the Xe3P GPU microarchitecture, with the D270 being the highest-end SKU. The company's website has added a GPU bare die shot, revealing that the card is not the massive chip one might expect, but rather something seemingly smaller. The D270 GPU SKU features 32 Xe3P cores, 256 XMX engines, and 32 MB of unified L2 cache; the XMX engines have been redesigned from the four-deep systolic design of the regular Xe3 to 16-deep processing on the Xe3P. The card is intended for AI inferencing rather than training, is rated for up to 480 GB of LPDDR5X, supports the FP4 data format alongside FP8, and has large register files of 1 MB per core and an L1 cache of 512 KB per core. In total there are 256 Vector engines and 256 of the new XMX engines, each divided into groups of eight per Xe3P core. Furthermore, the Xe3P lacks graphics processing elements for outputting imagery, as the silicon is designed purely for AI inference workloads that require long context and agentic tasks; a media engine with four encoders and four decoders is also included, which could assist with multimodal workloads where video generation and understanding are essential.
Intel has agreed to acquire Classiq, an Israeli developer of quantum computing software. The deal would combine Classiq's software with Intel's own silicon spin qubits and manufacturing, turning Intel's Quantum Computing Group into a full-stack business; Intel CEO Lip-Bu Tan said joining forces with Classiq transforms the group into a full-stack quantum computing business. Classiq, based in Tel Aviv, has developed a platform for automated synthesis of quantum algorithms, and the software works independently of the underlying hardware and qubit type. With the acquisition, Intel also plans to add quantum processing units (QPUs) to its portfolio of CPUs, GPUs and ASICs, and says it will continue to support Classiq's existing integrations with other hardware platforms after the deal closes. The deal is expected to close in the first half of 2027, subject to regulatory approvals; the companies have not disclosed the purchase price.
quantum computing softwaresilicon spin qubitsquantum processing units (QPUs)Intel, ClassiqEvertiqPartnership/M&A
Per the September 2026 announcement, AnalogAI, a South Korean company specializing in edge AI processors, has selected memBrain SAGE (Synaptic Analog Generative Engine) neuromorphic hardware IP from Silicon Storage Technology (SST), a Microchip subsidiary, for its first real-world edge AI processors, targeting inference with on-device adaptation to changing real-world conditions at a power consumption of one watt or less; the article notes it is early days for AnalogAI's processors, and the source does not state the cause of any price or supply impact. AnalogAI is SST's fourth publicly announced memBrain licensee, following Witmem in February 2022 (low-power speech processing), Intelligent Hardware Korea in September 2023 (analog compute platforms for edge AI, particularly computer vision), the October 2024 announcement by GlobalFoundries, Witmem and Microchip of sampling of Witmem's WTM-8 video processor capable of 8K video at 120 frames per second, and Mythic's March 2026 selection of memBrain technology for its next generation of ultra-low-power analog processing units. The technology is built on SST's embedded SuperFlash memory using established 40nm and 28nm foundry processes; in SST's YOLOv5 comparison example, the aCIM implementation processes 150 frames per second at 3 watts versus the GPU-based implementation's 200 frames per second at 60 watts, or roughly 15 times the energy efficiency (the THUS AI audio chip in Anker's Soundcore Liberty 5 Pro earbuds also uses this technology, with underlying silicon supplied by Witmem).
flash memoryedge AI processorsAnalogAI, Silicon Storage Technology and 3 totalEE JournalPartnership/M&A
On October 21, during GTC Berlin, Nvidia announced several multi-billion-dollar deals with six major supply chain partners — Ibiden, Unimicron, Samsung Electro-Mechanics, SPIL, Amkor and KYEC — across substrates, advanced packaging, semiconductor testing and optical engines, to expand production capacity and reserve capacity for its AI accelerators; expanded supply is to be available from 2027 through 2028, with commitments and production roadmaps stretching through 2028. For substrates, Nvidia plans to secure 2.5x dedicated substrate capacity over the next three years: it earlier signed a deal to provide a multibillion-dollar capacity reservation advance to support Ibiden's Ono Plant in Japan (targeting 3x the plant's current capacity); the Samsung Electro-Mechanics deal will support facility upgrades and new plants in Busan and Sejong, with Nvidia projected to account for a significant portion of its output by 2028; a capacity reservation agreement with Unimicron supports its substrate expansion in Taiwan, expected to start providing capacity by Q2 2027 and reach full capacity by mid-2028. For co-packaged optics, Nvidia signed with SPIL to expand optical engine production capacity 15x (1,400%) by mid-2027, with plans to double again by the end of 2028. With Amkor, Nvidia targets a more-than-300% increase in interposer wafer capacity by the end of 2028 through advanced packaging expansion in South Korea; Amkor confirmed the deal is worth $1.3 billion, bringing Nvidia's total investment across Amkor's Arizona and South Korea facilities to $3 billion. For testing, on October 13 Nvidia signed a deal to pay KYEC $1.1 billion to reserve testing capacity at KYEC's new $1.4 billion U.S. facility (high-volume production slated to begin in April 2027; Singapore high-volume production expected to begin February 2027), with testing capacity expected to double from calendar 2026 to 2027; KYEC currently handles nearly all of Nvidia's chip testing. Per its August 2026 disclosures, Nvidia had accumulated $279 billion in outstanding supply and manufacturing-capacity commitments by July 2026. All expansion figures are announced plans and targets, not yet realized.
substratesadvanced packaginginterposer wafersNvidia, Ibiden and 7 totalTom's HardwareCapacity Change
Micron has announced that G11 will be its first 3D NAND Flash and is actively working on bringing its next-generation G11 NAND technology to production. Its current G9 technology is shipping across Micron's product portfolio with over 200 layers of scaling; as the current technology reaches its limitations, Micron aims with G11 to use wafer-on-wafer 3D NAND stacking to double the capacity of NAND modules, splitting each wafer into a memory cell wafer and one containing peripheral logic circuits, combined via hybrid bonding technology. Micron plans to ship 400-layer NAND in the second half of 2027. The source also notes that Chinese NAND maker YMTC has been making 3D stacked NAND for some time using Xtacking technology. This is a plan, not an achieved result.
South Korean memory chip designer Jeju Semiconductor is struggling to secure enough wafer capacity from Taiwan's Powerchip Semiconductor Manufacturing (PSMC), which is limiting its sales growth. The stated cause is that strong memory demand is driving up prices and manufacturing costs. No specific figures, percentages, or dates are provided, and the source does not state whether PSMC will expand capacity or adjust allocation.
Per an October 27, 2026 report: Japan's Rapidus Corporation and Indian technology firm HCLTech have inaugurated two HCLTech development centers in India dedicated to supporting Rapidus' evolving semiconductor engineering requirements. The centers, located in Bengaluru and Hubli, will leverage HCLTech's expertise in core engineering to offer Rapidus a range of semiconductor engineering capabilities, including mask design, design infrastructure, process design kit development, design technology co-optimization and layout design. HCLTech will also collaborate with Rapidus to build a pipeline of Indian engineering talent to meet Rapidus' evolving talent requirements in Japan. Rapidus CEO Dr. Atsuyoshi Koike said building a strong engineering ecosystem is essential as Rapidus advances its mission to establish next-generation semiconductor manufacturing capabilities in Japan, and that through this collaboration Rapidus expects to access India's growing pool of semiconductor engineering talent and establish dedicated development capabilities that complement its operations in Japan. HCLTech CEO C Vijayakumar said the partnership reflects the growing strategic collaboration between Japan and India. Apart from these statements from both companies, the source does not state the cause.
During its third-quarter earnings call held on Oct. 26 local time, Cadence Design Systems raised its full-year revenue forecast to between $6.387 billion and $6.417 billion, implying 21% year-on-year growth, up from the 19% growth forecast issued with its second-quarter results. The company reported third-quarter revenue of $1.63331 billion, up 22% from a year earlier; non-GAAP operating margin excluding one-time costs was 44.1%; non-GAAP EPS rose 9% to $2.11; and backlog reached a record $8.2 billion at the end of the quarter. Cadence unveiled Maestro, a family of AI models specialized for semiconductor and system design, based on open-weight models post-trained using Cadence's design tools and data, saying initial results showed up to a 30% improvement in design quality and up to a fivefold improvement in token efficiency compared with general-purpose foundation models; it plans to integrate Maestro with its AI design agents including ChipStack, InnoStack and AuraStack. CEO Anirudh Devgan said that two decades ago IBM and Intel needed 500 engineers working for five years to design a single CPU, versus 50 engineers working for six months today, that chip design has become roughly 100 times easier, that AI could deliver an additional five- to tenfold efficiency gain, and that the combined improvements could make chip design 1,000 times easier than 20 to 25 years ago; he also said about 45% of the company's business comes from non-semiconductor companies. Samsung Foundry adopted InnoStack in the third quarter to improve the efficiency of process migration and design technology co-optimization (DTCO); Renesas Electronics' MCU development team achieved a 34-fold productivity improvement by applying InnoStack to multiple tasks and plans to extend its use to layout automation; MediaTek integrated ChipStack into its production digital verification flow, increasing verification coverage by 50% to 70% while reducing engineering workloads by 1.4 to 2 times. CFO John Wall said AI agents can generate and run far more design iterations than engineers manually operating the tools, potentially driving a substantial increase in EDA tool consumption.
The source does not state a specific date. According to the source, expanding investment in AI data centers is putting pressure on memory supply and demand across the automotive industry. As semiconductor companies prioritize high-bandwidth memory (HBM) and server products, automotive memory faces rising prices and tighter supplies. Against this backdrop, automakers' direct procurement, long-term partnerships, and in-house chip design are becoming increasingly strategic. No specific price change magnitude or figures are given in the source.
Fujifilm Electronic Materials is planning to expand its advanced semiconductor materials capacity in South Korea, specifically increasing extreme ultraviolet (EUV) photoresist capacity in Pyeongtaek and expanding chemical mechanical polishing (CMP) slurry production in Cheonan. The investments will deepen local support for customers including Samsung Electronics, which the source attributes to growing AI and advanced-process demand. This expansion is in a planned status; the source gives no specific investment amount or timeline.
Applied Materials plans to increase its stake in Dutch semiconductor equipment maker BE Semiconductor Industries (Besi) to approximately 20% from 9%, deepening its involvement in advanced chip packaging as demand for hybrid-bonding equipment accelerates. The stake increase is a plan; the source does not state the cause.
hybrid-bonding equipmentApplied Materials, BE Semiconductor Industries (Besi)DigiTimes AsiaPartnership/M&A
Related manufacturers
Applied Materials, BE Semiconductor Industries (Besi)
The source reports that the rapid expansion of AI data centers is driving demand beyond GPUs, memory chips, and advanced packaging. As power consumption in GPU clusters rises, data centers need not only more chips but also more efficient power delivery systems. Power plants and electrical grids outside data centers are also under pressure to close supply gaps, which could potentially tighten power semiconductor supplies and spread shortages to other applications. The source does not name specific manufacturers, part numbers, quantities, or dates, and describes the shortage only as a potential risk rather than a confirmed shortage.
HCLTech and Japan's Rapidus have inaugurated development centers in Bengaluru and Hubli, India, expanding their semiconductor engineering collaboration across Asia. The facilities will support advanced chip work, while a planned talent pipeline could connect Indian engineers with Rapidus' manufacturing ambitions in Japan, highlighting the cross-border partnerships shaping semiconductor supply chains.
Anthropic filed a preliminary IPO registration statement with the US Securities and Exchange Commission, in which it describes how much of its capacity depends on a small group of chip and memory suppliers, most of them in East Asia. The filing puts TSMC, HBM and direct leasing at the center of its AI compute risk disclosure. This is a risk statement in a preliminary registration document; it does not report any capacity change, halt or price movement.
India's semiconductor drive has largely been led by New Delhi, which selects projects for large central incentives, while state governments add their own packages of land, infrastructure and financial support. Tamil Nadu is now giving semiconductor investors another route, described in the title as an independent chip subsidy route. The source does not state further details, implementation conditions, or the cause behind this move.
Applied Materials plans to increase its stake in Dutch company BE Semiconductor Industries (BESI) from 9% to approximately 20%, deepening a partnership focused on advanced packaging technologies for AI chips. The transaction is structured through an accelerated share purchase agreement and is subject to U.S. antitrust review; the company said it does not intend to increase its stake beyond approximately 20% or seek representation on BESI's board. Applied Materials became BESI's largest shareholder after acquiring a 9% stake in April 2025; the two companies have collaborated on hybrid bonding technology since 2020 and jointly developed Kinex, an integrated die-to-wafer hybrid bonding system. According to ijiwei, BESI holds approximately 70% of the global hybrid bonding equipment market. According to Reuters on October 22, BESI's third-quarter orders rose 96% year over year to €342.6 million, and hybrid bonding equipment orders in the first nine months of 2026 more than doubled compared with the full-year 2025 level; BESI's latest earnings release shows its hybrid bonding customer base has expanded to 23, with cumulative equipment demand exceeding 215 systems. According to ijiwei, Chinese equipment maker Piotech generated RMB 136 million in hybrid bonding equipment revenue in 2025, up 41.92% year over year, and secured repeat orders for its wafer-to-wafer hybrid bonding systems.
hybrid bonding equipmentKinex die-to-wafer hybrid bonding systemDatacon 8800 CHAMEO ultra plus AC systemApplied Materials, BE Semiconductor Industries (BESI) and 3 totalTrendForcePartnership/M&A
Related manufacturers
Applied Materials, BE Semiconductor Industries (BESI), Piotech
Cadence Design Systems is betting that chipmakers will want AI models trained on its own design tools and run wherever customers choose, putting it on a different route from rival Synopsys, which is building its specialized model with OpenAI on OpenAI-hosted infrastructure. On October 26, alongside its third-quarter results, Cadence introduced Maestro, a portfolio of domain-specialized AI models that power its AI super agents for chip and system design.