S2C Targets Faster RISC-V Bring-Up With Prototyping and AI

What happened

S2C showcased FPGA prototyping and AI-assisted debugging at the sixth RISC-V Summit China (October 18–20, Shenzhen Convention and Exhibition Center). In its booth demonstration, an Andes Technology AX66-based RISC-V configuration ran Linux KVM on S2C's Prodigy S8-100 FPGA prototyping system, using 55% of the resources available on a single AMD Versal Premium VP1902 FPGA; the source states this demonstration and utilization figure should not be read as measurements of final silicon performance or application throughput. S2C also demonstrated RCF Agent using RTL from the open-source XiangShan RISC-V processor; the agent starts compilation, gathers error messages, and generates an initial analysis, but the demonstration concerned initial analysis only and did not establish that the agent independently resolves every error or replaces engineering review. In the summit's chip design and verification forum, S2C presented "LLM-based RISC-V Virtual Platform & Debug Flow," a proposed workflow combining a virtual platform modeling the processor, memory, buses, interrupt controller, and common peripherals with an LLM-assisted layer that interprets captured debug information; the platform can boot firmware, bootloaders, and operating systems and supports breakpoints, watchpoints, state inspection, and execution tracing. The source does not state the cause (no cause-related event).

Impact and signal

Affected components and suppliers

Source and time

Source: SemiWiki · 10/27/2026 · View original source