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Cadence

NuAxi groups public briefings that mention Cadence: product launches, capacity and pricing signals, and supply-chain changes. The page updates continuously.

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Fri, Oct 30

  1. Impact score 30

    SEMICON West 2026: AI Made the Steps Faster. The Time Between Them Is Next.

    Conference report from SEMICON West 2026: SEMI President and CEO Ajit Manocha told the CEO Summit that the semiconductor industry crossed $1 trillion in annual revenue this year, almost four years ahead of earlier projections; a year ago the forecast for 2030 was $1 trillion, now it is $2 trillion, with $3 trillion possible by 2035; the industry has 102 new fabs coming online through 2029 and needs more than 50 beyond that by 2035. Synopsys CEO Sassine Ghazi named the shortage of engineers as the industry's challenge, and Brooks Automation CEO Dave Jarzynka noted a wafer spends only about 25% of its time in the fab actually being processed. In the design session "Bridging Design and Manufacturing with AI" on Tuesday, October 13 in Room 20 at Moscone North, speakers from TSMC, Intel, Applied Materials, Lam Research, Cadence, Silvaco, PDF Solutions, McKinsey, Cerebras, SanDisk and VerifAIX covered seven themes. Specific figures include: Intel's DTCO decisions dropped from weeks to one or two hours; Applied Materials cut a 3D gate-all-around device simulation from 20.5 days to 19.7 hours on GPUs; McKinsey showed AI-assisted programs reaching tape-out nine months after design starts and cutting debug closure time by 40%; TSMC's agentic place-and-route runs around the clock at 3 to 5x productivity; Rhines showed NAND process steps rising from about 400 to as many as 1,800, wafer lot cycle time stretching from 8 to 10 weeks at 28nm to 16 weeks or more, and mask sets climbing from $1 to 3 million to $20 to 40 million or more; VerifAIX cited first-silicon success at 14% and the best AI pass rate on hardware code generation at 34%; PDF Solutions' Kimon Michaels cited Qualcomm's engineering and manufacturing data growing 600% since 2022, while less than 5% of manufacturing data gets analyzed; Lam's research published in Nature found engineers and algorithms working together, with the handoff in the right place, cut the cost of reaching a process target in half. The session also covered co-optimization (DTCO/STCO) replacing sequential handoffs, trust issues in autonomous design, and digital twins changing development. This is a conference recap and industry background; the source does not state the cause (no single event cause).

    NAND3D gate-all-around deviceCFETTSMC, Intel and 16 totalSemiWiki

Tue, Oct 27

  1. Impact score 60

    Cadence Raises Annual Revenue Forecast as AI Boosts Chip Design Productivity

    During its third-quarter earnings call held on Oct. 26 local time, Cadence Design Systems raised its full-year revenue forecast to between $6.387 billion and $6.417 billion, implying 21% year-on-year growth, up from the 19% growth forecast issued with its second-quarter results. The company reported third-quarter revenue of $1.63331 billion, up 22% from a year earlier; non-GAAP operating margin excluding one-time costs was 44.1%; non-GAAP EPS rose 9% to $2.11; and backlog reached a record $8.2 billion at the end of the quarter. Cadence unveiled Maestro, a family of AI models specialized for semiconductor and system design, based on open-weight models post-trained using Cadence's design tools and data, saying initial results showed up to a 30% improvement in design quality and up to a fivefold improvement in token efficiency compared with general-purpose foundation models; it plans to integrate Maestro with its AI design agents including ChipStack, InnoStack and AuraStack. CEO Anirudh Devgan said that two decades ago IBM and Intel needed 500 engineers working for five years to design a single CPU, versus 50 engineers working for six months today, that chip design has become roughly 100 times easier, that AI could deliver an additional five- to tenfold efficiency gain, and that the combined improvements could make chip design 1,000 times easier than 20 to 25 years ago; he also said about 45% of the company's business comes from non-semiconductor companies. Samsung Foundry adopted InnoStack in the third quarter to improve the efficiency of process migration and design technology co-optimization (DTCO); Renesas Electronics' MCU development team achieved a 34-fold productivity improvement by applying InnoStack to multiple tasks and plans to extend its use to layout automation; MediaTek integrated ChipStack into its production digital verification flow, increasing verification coverage by 50% to 70% while reducing engineering workloads by 1.4 to 2 times. CFO John Wall said AI agents can generate and run far more design iterations than engineers manually operating the tools, potentially driving a substantial increase in EDA tool consumption.

    EDA toolsCadence Design SystemsThe Elec
  2. Impact score 0

    Cadence says chip design demand is broadening beyond AI as analysts test margins, rival targets

    Cadence Design Systems used its third-quarter earnings call to argue that demand for chip design tools is no longer tied only to the AI hardware buildout, pointing to analog and memory chipmakers, system companies, and new entrants such as space and finance firms designing their own silicon. On the October 26 call, analysts pressed two questions that will shape the coming year: how much growth comes from agentic AI rather than hardware, and whether Cadence can match the long-term targets rival Synopsys set a month earlier.

    chip design toolsCadence, SynopsysDigiTimes Asia
  3. Impact score 58

    Cadence raises 2026 outlook as AI design demand drives record backlog

    Cadence Design Systems said revenue for the three months ended September 30, 2026 rose 22% from a year earlier, with the results announced on October 26. The company said AI-driven design work is showing up in both revenue and backlog, with backlog at a record level, and it raised its 2026 outlook (a forecast/guidance, not an achieved result). The company also said the cost of buying growth is hurting profitability, while operating income barely moved.

    chip design toolsCadence Design SystemsDigiTimes Asia

Mon, Oct 19

  1. Impact score 10

    A Composable Thermal Solver For Heterogeneous 2.5D/3D-IC Packages (Cadence, Notre Dame)

    Researchers at Cadence Design Systems and the University of Notre Dame published a research paper titled "A Composable AI-Accelerated Iterative Solver for 3D-IC Thermal Modeling." According to the abstract, accurate thermal analysis of heterogeneous 2.5D/3D-IC packages is essential yet computationally prohibitive; a single full-package FEM simulation can take hours, while AI-based surrogates treat the entire stack as a monolithic prediction target. This is a research publication and background information only, with no price, capacity or supply event involved.

    3D-IC thermal modeling2.5D/3D-IC packagesCadence Design Systems, University of Notre DameSemiconductor Engineering

Fri, Sep 11

  1. Impact score 45

    EMA, FlowCAD acquisitions expand Cadence’s PCB design portfolio

    Cadence acquires EMA Design Automation and FlowCAD to integrate their PCB design technologies into the Allegro X and OrCAD X platforms. This strategic expansion enhances component data management capabilities. Impact: Neutral for component pricing; Watch for EDA market consolidation.

    Allegro XOrCAD XUltra LibrarianCadence, EMA Design Automation and 3 totalEvertiqPartnership/M&A

Thu, Jul 23

  1. Impact score 10

    Agentrys Weighs in on LLM Benchmarking for Chip Design at DAC 2026

    Si2 and industry leaders including Nvidia, Cadence, and Synopsys are establishing standardized benchmarks for LLMs in chip design at DAC 2026. This initiative aims to create consistent evaluation methods for AI agents in Electronic Design Automation (EDA) workflows. The move supports long-term AI adoption in semiconductor design but has no immediate impact on component pricing or supply.

    Nvidia, Normal Computing and 5 totalSemiWikiTechnical

Fri, Jul 17

  1. Impact score 45

    Chip Industry Week In Review

    This week's semiconductor industry highlights include Intel expansion, CHIPS Act funding, HBM standardization, and Rapidus collaboration. These events reflect policy support and capacity expansion trends, though specific price data is absent.

    HBMPCBIntel, Cadence and 4 totalSemiconductor EngineeringPolicy/Regulation

Tue, Jul 14

  1. Impact score 10

    Electronic System Design Industry Revenue Up 13% in 1Q 2026

    The Electronic Design Automation (EDA) industry reported 13% year-over-year revenue growth in Q1 2026, indicating robust demand for design tools.

    Synopsys, Cadence Design Systems and 4 totalEE Times AsiaMarket Analysis

Sat, Jul 11

  1. Impact score 10

    Alok Jain: The Engineer Who Never Wanted to Be a Manager

    Alok Jain has transformed Cadence India into a chip-design powerhouse and is focusing on AI as the next growth area. This highlights the strategic shift of design capabilities to India and Cadence's long-term outlook.

    Cadence Design SystemsEE TimesMarket Analysis

Fri, Jun 12

  1. Impact score 15

    Cadence, Samsung Foundry Expand 2nm and 3D‑IC Platform Partnership

    Cadence and Samsung Foundry are expanding certified 2nm and 3D-IC design capabilities for AI infrastructure systems.

    2nm3D-ICSamsung Electronics, Cadence Design SystemsEE Times AsiaPartnership/M&A

Thu, May 28

  1. Impact score 10

    Quantum Simulation Using Decision Diagrams. Innovation in Verification

    Researchers propose using Quantum Multi-Valued Decision Diagrams (QMDD) to simplify quantum circuit simulation, addressing exponential complexity. This represents a technical advancement in EDA and verification, though it currently has no direct impact on spot prices or supply.

    Cadence, SynopsysSemiWikiTechnical

Wed, Apr 1

  1. Impact score 5

    What is the EDA problem worth solving with AI?

    EDA industry is heavily hyping AI, but major customers like Samsung and Nvidia are building their own internal AI stacks. The article notes current progress focuses on optimizing legacy workflows rather than solving core verification problems. Watch: EDA tool vendors face competitive pressure from internal solutions, but price impact is currently neutral.

    EDA ToolsCadence, Synopsys and 5 totalEDNMarket Analysis

Wed, Mar 18

  1. Impact score 25

    Cadence and NVIDIA Expand Collaboration to Accelerate Agentic AI Chip and System Design Solutions

    Cadence is expanding its collaboration with NVIDIA to accelerate AI chip and system design solutions. This strategic partnership focuses on Design for AI and AI for Design capabilities, signaling strong demand for advanced semiconductor design tools.

    EDA ToolsAI ChipsCadence, NVIDIAEE Times AsiaPartnership/M&A

Thu, Mar 12

  1. Impact score 15

    [News] SerDes Wars Heat Up: Broadcom, Marvell, MediaTek Battle for AI Interconnect Supremacy

    Competition in high-speed SerDes technology intensifies as AI models drive demand for chip-to-chip interconnect bandwidth. MediaTek reportedly entered Google's TPU ecosystem with its 224G SerDes, while NVIDIA is opening its NVLink Fusion SerDes IP to partners. Neutral: This is a long-term technology landscape shift with no immediate, specific impact on component supply, pricing, or production.

    SerDes IPAI InterconnectBroadcom, Marvell and 6 totalTrendForceMarket Analysis

Mon, Mar 9

  1. Impact score 10

    Examining Cadence’s Physical AI Chiplet Platform

    Cadence announced a chiplet platform aimed at supporting physical AI hardware development. This is a design tool and methodology announcement from an EDA software vendor, not a hardware supply chain event. Neutral: No immediate impact on component supply, pricing, or procurement.

    AI ChipletCadence Design SystemsElectronic DesignTechnical

Tue, Feb 24

  1. Impact score 42

    Cadence completes acquisition of Hexagon’s D&E business

    Cadence Design Systems completed its EUR 2.7 billion acquisition of Hexagon's Design and Engineering business, integrating MSC Software's structural analysis portfolio. The deal aims to create an end-to-end multiphysics simulation platform for system design. Watch: This vertical software integration has no direct impact on component supply, pricing, or availability.

    EDAMultiphysics Simulation SoftwareCadence Design Systems, Hexagon ABEvertiqPartnership/M&A

Thu, Feb 19

  1. Impact score 60

    [News] China Reportedly Ramps Up Chip Tool Push, Sets 70% Target by 2027; SMEE, NAURA at Forefront

    China has set a target to source 70% of equipment for mature-node chipmaking domestically by 2027, with domestic toolmakers like SMEE and NAURA making progress in 28nm lithography and etching. This aggressive localization push is a direct response to U.S. sanctions and aims to reduce reliance on foreign suppliers.

    利空

    This policy is bearish for leading non-Chinese semiconductor equipment manufacturers, as it signals a structural, long-term reduction in demand from a major market, potentially leading to oversupply and pricing pressure for mature-node tools.

    Semiconductor Manufacturing EquipmentLithography SystemsEtch ToolsASML, Applied Materials and 6 totalTrendForcePolicy/Regulation

Tue, Feb 10

  1. Impact score 15

    Cadence’s HiFi DSP Purpose-Built for Next-Gen Voice AI and Audio

    Cadence has launched its HiFi iQ DSP, a purpose-built processor for next-generation voice AI and audio applications. The launch positions the IP as a key building block as tech giants push for voice to become a dominant AI interface. Neutral: This is a new IP product launch with no immediate, direct impact on component supply, demand, or pricing for traders.

    DSPAudio CodecCadence Design SystemsElectronic DesignProduct Launch