High-side switch thermal and line-fuse coordination: from thermal feedback to fault clearing

1. Separate verified device boundaries from unproven system capability

This extends the automotive protection-switch guide rather than repeating general entry-versus-branch selection. The deliverable is a current-time-temperature coordination envelope: initial temperature, load waveform, switch action, post-trip current tail and permitted recovery for each path. The IC, wire, connectors, fuse and upstream power stage have different thermal time constants; one temperature or I²t value cannot stand in for all of them.

Verified below means supported by the TI document and its stated conditions. System deductions and the bench plan are engineering methods in this article, not TI approval of a wire size, fuse, PCB or load combination. Sources are official full datasheets or application guidance; a summary and a curve in the same TI document are not independent validation.

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2. Establish the real heat path, then separate steady state from pulses

SPRA953D defines θJA through the package, test board and environment, not as an invariant material property of the IC. Pad/solder coverage, copper layers/area, thermal vias, neighboring dissipation, airflow and enclosure change effective θJA. A first steady-state estimate is TJ≈TA+θeff×P, but θeff must come from a model or measurement for the relevant construction, and TA needs a defined local measurement position. Renaming a standard-board value does not make it measured system data.

For a fully enhanced switch, budget at least ΣIk²RON,k(TJ)+Pother, including configuration-dependent quiescent, diagnostic and switching losses in Pother. Integrate I² for PWM conduction loss rather than squaring average current. During linear startup, clamp turn-off or faults, use p(t)=VDS(t)×I(t). Package-top temperature is not junction temperature. SPRA953D's ψJT is a characterization parameter, not a true thermal resistance; use it to estimate junction temperature from measured package-top temperature only after evaluating applicability and measurement uncertainty, rather than multiplying total power by θJC(top).

Both HB16 datasheets provide transient thermal-impedance curves in §10.1.7 for a standard 2s2p board. If Zθ(t) is the power-step response, a rectangular incremental power pulse from initial thermal equilibrium gives ΔTJ(tP)=Ppulse×Zθ(tP). In an applicable linear thermal model, multiple power steps can be summed as ΣΔPk×Zθ(t−tk), including a negative step at turn-off. Nonrectangular power and temperature-dependent RON need a time-domain model or piecewise iteration. Repeated pulses must retain residual heat instead of restarting every event at TA.

The RC-network and RON-feedback methods in SLVAEZ0 are useful, but §5 limits the model to nominal silicon and a JEDEC board, and only some device models include thermal behavior. This article has not validated a downloadable model against a board. Nor does it transfer other devices' constant-current charging behavior in SLVAE30E to HB16 overcurrent shutdown.

3. Bounded worked example: solve hot resistance and temperature together

This hypothetical board-level model demonstrates algebra, not TPS1/TPS2 rated capability. Assume local TA=80°C, a constant 5 A per active channel and one simplified shared temperature node. Assume θeff=40°C/W and total Pother=0.10 W; neither is a measurement. Also assume R80=25 mΩ and R(T)=R80×[1+α(T−80°C)], with α=0.004/°C, used only over this example's 80–150°C interval. R80 and α are not extracted TI typical-curve values or guaranteed maxima, and these assumptions do not represent production variation.

Let ΔT=T−80°C and n be the active-channel count. Then ΔT=θeff×{nI²R80[1+αΔT]+Pother}. Rearranging gives ΔT=θeff(nI²R80+Pother)/(1−θeff nI²R80α), where β=θeff nI²R80α is dimensionless thermal feedback. Calculate β and temperature, then substitute back into R and P instead of leaving resistance at its cold value. If the denominator is nonpositive or the result leaves the assumed fit interval, reject this model solution and redesign/remodel; that is not proof that the physical device must run away, nor permission to rely on shutdown.

Under these assumptions, one channel reaches about 112.22°C; two at 5 A each reach about 147.50°C because total loss also raises resistance. With two channels, each has R≈31.75 mΩ and about 0.794 W conduction loss, giving 1.6875 W total including Pother. Incorrectly freezing R at 16 mΩ instead gives 0.8 W conduction loss and 116°C on the same hypothetical board. It underestimates this model's temperature, not a measured board's error. The 0.4 W figure is only the multiplication for one 5 A channel at the 25°C typical 16 mΩ.

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4. Shared-package coupling does not mean both channels shut down together

The preceding single-temperature node illustrates feedback; it is not the TPS2HB16 internal thermal model and cannot predict absolute/relative thermal-shutdown thresholds. FET1, FET2 and the controller occupy different locations. Section 9.3.1.1 evaluates each FET's absolute temperature and difference from the controller. If only one channel's sensor triggers, only that switch turns off and the other keeps operating. Shared package/PCB heat or supply disturbance can still reduce the other channel's margin; measure this rather than treating independent fault logic as thermal isolation.

A better steady-state representation is ΔT1=θ11P1+θ12P2 and ΔT2=θ21P1+θ22P2, also accounting for the controller, neighbors and boundary temperatures. Diagonal terms describe self-heating and off-diagonal terms cross-heating. These are not arbitrary datasheet constants; identify them through a structural model or controlled power steps. Use corresponding Z11(t), Z12(t) terms for transients. TPS2 §10.1.7's single-channel and evenly loaded dual-channel curves have different conditions and do not constitute a complete asymmetric coupling matrix.

Cover one-channel steady state, both-channel steady state, one channel starting while the other is already hot, staggered versus simultaneous startup, and the healthy channel after a bounded fault pulse. Staggering can reduce some peaks, not the total heat of long-term simultaneous operation. Both channels eventually at full load still require the two-channel steady-state check. The example's 147.50°C is not a temperature guarantee; subtracting it from a rating without board-model and production uncertainty cannot establish a pass.

5. Coordinate wire and fuse uncertainty bands, not ampere labels

Overlay normal/startup waveforms, earliest/latest electronic-protection envelopes, fuse melting/total-clearing curves and minimum wire/connector withstand envelopes on the same time-current axes. Obtain the specified fuse's temperature rerating, pulse endurance, time-current range, minimum melting and maximum total-clearing data, applicable voltage and interruptible fault current. A typical curve does not justify invented guaranteed bounds. Harness evidence also needs insulation, initial temperature, bundling and installation cooling. No wire cross-section or fuse rating is prescribed here.

S=∫I²dt has units A²s, not joules. Joule heat requires conductor resistance: ∫I²R(T)dt. I²t is useful for short, approximately adiabatic events; slower overloads need the wire thermal model and fuse time-current curves, not a short-circuit constant extrapolated to any duration. SDAA247 §2.3 separates melting from arcing: downstream protection needs total clearing, not melting alone. Section 2.4 also describes specified opening-time ranges for some conditions, so neither all curves are guarantees nor all fuses lack guaranteed data.

If the goal is electronic clearing of a recoverable branch fault while retaining the upstream fuse, prove that the latest electronic clearing envelope—including detection, turn-off and current tail—precedes both the earliest fuse-melting envelope and minimum harness-damage envelope with uncertainty margin. If the switch fails conducting or a fault is upstream of it, independently prove backup-fuse maximum total clearing for that wire segment. Battery, wire/contact resistance, inductance and fault location determine actual current. Upstream current limiting can keep a fuse outside its guaranteed opening region indefinitely; eventual melting is not automatic.

A shared upstream fuse sees IΣ=I1+I2+Iother, so its I²t is ∫IΣ²dt, not the sum of branch I²t values; simultaneous currents introduce cross terms. Conversely, a local output-capacitor discharge may bypass that fuse. Integrate each actual current path, including slow overloads below the electronic trip threshold that can still overheat wiring. An IC that never reaches thermal shutdown does not prove that a remote connector stays cool.

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6. Treat inrush, trip delay, retry and demagnetization as one event

HB16 A/B/F variants select different current-limit thresholds, not continuous-load classes. A/B resistor settings also require KCL and resistor tolerances; F's fixed high threshold is not a continuous-current promise. Section 9.3.1.2 specifies channel shutdown at ICL, with fast current rises able to overshoot because of deglitch and turn-off time. Its 3 µs deglitch description is neither a programmable inrush allowance nor a complete maximum clearing time. Do not deliberately fit startup inside that interval or reinterpret the threshold as sustained constant-current charging.

For legitimate capacitive startup, derive the current envelope from I=C×dV/dt plus operating load, then check the minimum threshold and actual startup timing. For faults, use the maximum threshold, worst response delay and measured peak envelope. As integration arithmetic only, assume total line current is exactly 8 A for 5 ms with no tail: S=8²×0.005=0.32 A²s. The 5 ms is not an HB16 timing specification, 8 A is not a recommended setting, and the result selects no fuse. Recalculate the entire waveform if there is a tail or background load.

Three identical hypothetical pulses total 0.96 A²s of raw integration, but that does not predict certain fuse melting: cooling, preheating and pulse endurance matter. The switch likewise needs two budgets: Eevent=∫VDSI dt for each event's transient stress, and Eevent/Trep for average added power at repetition interval Trep. The latter does not bound local peak junction temperature. Check LATCH, EN, tRETRY and variant-specific foldback against the complete part number. B-variant threshold reduction after repeated faults is not a substitute for system retry-count and cooldown policy.

A turn-off command does not make energy disappear. Load and harness inductance sustain current; ½LI² is initial magnetic energy, not necessarily the energy ultimately absorbed by the switch, since the supply may add energy during clamping. Measure VDS, current and demagnetization time in the actual clamp/freewheel path, checking initial temperature and repetition. External freewheel or TVS paths change release time and whether current passes through the fuse. SLVAE30E §4.5 supplies the method, not permission to transfer another part's demagnetization curve or single-event capability to HB16.

7. LM7480: place the thermal budget on the external MOSFETs

LM7480-Q1 controls external back-to-back MOSFETs; load current is not carried inside the controller. Evaluate each FET's I²RDS(on)(TJ,VGS), plus shunt, connector and copper losses. Do not multiply power-path loss by the controller's θJA. HGATE dV/dt capacitance changes the capacitive charging ramp but is not closed-loop short-circuit limiting. Check each FET's vendor SOA at actual VDS, ID, duration, duty cycle and starting temperature. Low RDS(on) or a large pulse-current headline does not establish linear-mode capability.

Distinguish overvoltage topologies: the usual battery-sensed OV configuration disconnects HGATE and does not imply a regulated output clamp, but the entire family cannot be described as incapable of clamping. SNOSD95C §10.3, Figure 10-25 explicitly presents an LM74800-Q1 common-source reference circuit. Section 10.3.2.4 uses a divider connection to VBATT for cutoff and to VOUT for output clamping. That example depends on external FETs, VS voltage limiting and TVS components; §10.3.2.5 specifically requires clamp-power and SOA margin. It does not permit applying 200 V directly to the IC or validate LM74801 or arbitrary wiring.

If upstream LM7480 disconnects first, the branch fuse may remain intact while output capacitance and inductive paths retain energy. With clamping, an external FET may sustain a voltage difference instead. Model these strategies separately, then assign overload/short-circuit responsibility, retry logging and recovery permission. Reverse-current control, OV cutoff and harness I²t protection are not one automatically completed function.

8. Include sensing error and blind intervals in the I²t envelope

HB16 SNS changes meaning between current, temperature and fault indication; retain the selection state and respect settling time before interpreting ADC data. It is not a simultaneous high-speed two-channel oscilloscope. A shunt with INA181-Q1 or INA241A-Q1 can provide an independent observation path, but still needs range, gain, bandwidth, ADC/reference, filter delay, shunt drift and saturation-recovery checks. Neither amplifier is itself a fuse or an independent disconnect actuator.

INA181 operates over −0.2 to 26 V common mode; placing it directly on a high-side node that can experience a 40 V load dump does not establish valid measurement. Design input protection and measurement location separately. The reviewed INA241A SBOSA31D specifies −5 to 110 V operating common mode, but negative inductive spikes can still exceed it, and survival limits are not accuracy limits. Its PWM-rejection behavior includes output hold during common-mode transitions. A held value is not the instantaneous current, and higher bandwidth alone does not eliminate missed microsecond events.

If Im=Itrue(1+ε) with proven |ε|≤e<1, no saturation and no missing samples, true I²t is conservatively bounded by Sm/(1+e)² and Sm/(1−e)², where Sm=∫Im²dt. Offset is not a simple percentage; first refer terms such as VOS/Rsh to a current interval. Clock error, filtering and uncaptured peaks also widen the bound. For offset-containing or signed-current intervals, take the largest possible |I| at each point before squaring, rather than adding only the gain-error percentage to the final integral.

9. Reversible bench workflow: establish bounds before increasing energy

This is a proposed validation workflow, not hardware testing completed for this article. Use a suitably equipped, qualified laboratory with an isolated energy-limited supply, electronic/emulated loads and appropriately rated instruments. Bench supply current limiting changes fault current; record that limitation instead of extrapolating directly to a low-impedance battery. This workflow does not require blowing a fuse, shorting a battery, bypassing protection, repeatedly reaching extreme thermal shutdown or destructive tests on a vehicle.

Make reversibility explicit: save the baseline configuration → de-energize and verify controlled discharge → change one variable → re-enable at lower energy → retain traces and stop reasons → de-energize, restore and verify the baseline. Power-stage or harness changes require renewed review; do not rewire energized hardware. If guaranteed supplier curves or safe energy bounds are missing, remain at calculation and low-energy functional checks rather than increasing test risk to complete a chart.

• Freeze full OPN, A/B/F, RILIM, default LATCH/EN states, PCB stack/copper/vias, enclosure, both loads and applicable fuse/harness supplier revisions; label missing items unverified.
• Predefine conservative current, pulse-width, temperature-proxy, accumulated-energy and retry-count stop limits from component/load specifications and model uncertainty; neither damage nor thermal shutdown is a completion criterion.
• At low energy, check zero, polarity, Kelvin shunt connections, VDS/current probe timing alignment, ADC saturation and SNS selection/settling; confirm there is no unintended backfeed path.
• Identify actual thermal response with low-power steps, recording local ambient, board/top temperatures and sensor uncertainty; increase load only within the budget and compare single/dual-channel stable results separately.
• Use controlled profiles for simultaneous/staggered startup and a preheated channel, without treating standard-board Zθ curves as board acceptance; record voltage, current, energy, enables and diagnostic timestamps.
• Only after risk review, use an energy-limited fault emulator to check shutdown/latch/bounded retries and the healthy channel; de-energize at stop conditions, with no indefinite retry or deliberate high-current hard short.
• Record turn-off tails and clamp paths with an already bounded low-energy inductive load, integrating until current truly reaches zero; higher-energy and backup-fuse failure testing require separately approved qualification.
• Overlay measurement uncertainty on electronic-clearing, fuse and harness curves; without earliest-melting, latest-clearing or wire-withstand evidence, claim neither selectivity, reduced wire size nor fuse removal.
• On exit disable retries, de-energize, verify stored-energy discharge and restore baseline wiring/configuration; retain failures and scope limits. One successful startup or absence of thermal shutdown does not replace system reliability/compliance validation.

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