Automotive current-sensing error budgets: shunt, amplifier, ADC and PWM

1. Common mode, supply, differential input and isolation are separate constraints

A millivolt shunt drop does not mean either input is only millivolts above ground. Record both input voltages during normal operation, reversal, PWM overshoot and power sequencing. Keep both pins within the specified common-mode range while checking differential and absolute-maximum limits separately. A wider common-mode range does not create a galvanic isolation barrier.

This guide uses INA241A-Q1 SBOSA31D Rev D: operational common mode is −5 to 110 V, not the older −4 V headline, and survival limits are not measurement limits. When shared INA241x documentation lists Grade 0, resolve it to an exact orderable. The reviewed Grade 0 condition explicitly belongs to INA241B3EDRQ1; it does not establish Grade 0 for the INA241A family.

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2. Keep offset, gain and output conditions together

INA181 section 6.5 defaults to TA=25°C, VS=5 V, VREF=VS/2 and VIN+=12 V. Maximum input offset is ±150 µV at VIN+=0 V and ±500 µV at the default 12 V common mode; do not transfer the low-side value to high-side sensing. The ±1% maximum gain error spans −40 to +125°C but requires VOUT from 0.5 V to VS−0.5 V. Near-rail output-swing specifications are not the same accuracy guarantee.

INA181 A1/A2/A3/A4 gains are 20/50/100/200 V/V, with typical small-signal bandwidths of 350/210/150/105 kHz at the datasheet's 10 pF load. The 350 kHz value belongs only to A1. INA241A initial offset/gain values below use 25°C, VS=5 V, VCM=48 V and both REF pins at VS/2; gain error additionally requires 50 mV<VOUT<VS−200 mV.

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3. Use range equations to constrain heat, gain and ADC together

Write the ideal relationships as Vsh=I×Rsh, Vout=Vzero+G×I×Rsh and Psh=I²×Rsh. Vzero is the zero-current output determined by REF wiring, not always zero. For bidirectional sensing, both endpoints must remain inside the amplifier's accuracy-qualified output range and the ADC input range. A 5 V amplifier feeding a 3.3 V ADC also needs overload-output and power-sequencing checks; nominal readings within range do not eliminate protection needs.

If the ADC measures raw Vout and software subtracts only nominal Vzero, a first-order worst-case budget is ΔI≈|I|×(|εR|+|εG|)+|εADC,gain|×|Vzero+G×I×Rsh|/(G×Rsh)+|VOS|/Rsh+(|ΔVzero|+|VADC,off|+q/2)/(G×Rsh), where q=VADC,FS/2ᴺ. ADC gain error acts on the entire biased output, not only the current signal. Temperature adds |I|×(|TCR|×ΔTR+|dG/dT|×ΔTA) and |dVOS/dT|×ΔTA/Rsh. Use dimensionless ε terms and convert ppm/°C drift to fractions; ΔTR is shunt temperature rise, not automatically ambient rise.

This is a reviewable first-order model; check the magnitude of omitted cross-products. If a limit already covers temperature, such as INA181's ±1% gain error, do not add the full temperature drift again for that same term. When combining a 25°C initial limit with separate drift, state the reference temperature. Separately budget CMRR, PSRR, reference transfer, input-filter mismatch, bias current, nonlinearity, noise, PWM disturbances and acquisition settling. RSS is appropriate only for independent random terms with a statistical model; taking the root-sum-square of datasheet maxima does not create a guaranteed limit. Near zero current, report absolute amperes rather than a divergent percentage.

4. Example: a precision amplifier can still be ADC-limited at 20 A

Assume INA241A3-Q1, G=50 V/V, Rsh=0.5 mΩ, bidirectional ±20 A, VS=5 V, both REF pins at 2.5 V, VCM=48 V and TA=25°C. Assume a shunt with ±0.1% initial tolerance and 25 ppm/°C TCR, and an ideal 12-bit, 5 V-full-scale ADC. Full-scale shunt drop is ±10 mV, output is 2.0–3.0 V, and shunt dissipation at 20 A is 0.2 W. This output lies inside the datasheet gain-error test range without borrowing a better offset from another gain variant.

ADC resolution is 5/4096=1.220703 mV per LSB, equivalent to 48.8281 mA per LSB or 24.4141 mA per half-LSB. The table sums only initial shunt error, amplifier offset/gain and ideal quantization. It is not a complete accuracy claim: reference and ADC gain/offset are assumed ideal, and noise, nonlinearity, common-mode changes and PWM are omitted. Fill those terms in a real design rather than presenting the subtotal as instrument certification.

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5. Temperature and low current change the dominant error

Continue the example with a separate conservative budgeting assumption: amplifier and shunt both rise from 25°C to 125°C, using first-order accumulation of the stated maximum drifts. INA241A3 offset drift contributes 0.1 µV/°C×100°C/0.5 mΩ=20 mA. At 20 A, gain drift contributes 20×1 ppm/°C×100°C=2 mA, and shunt TCR contributes 20×25 ppm/°C×100°C=50 mA. These three terms add 72 mA, bringing the listed subtotal to about 138.414 mA, or 0.6921% of 20 A, still excluding the omitted terms.

A real shunt can be hotter than the PCB because of I²R self-heating, and its thermal time constant differs from the amplifier's. Model ambient drift, self-heating and post-calibration residuals separately rather than forcing every component to one temperature. Initial zero/gain calibration can reduce repeatable static errors, but does not automatically remove subsequent thermal/reference drift or PWM common-mode-edge disturbances.

Keeping 0.5 mΩ and comparing only offset-equivalent current at each datasheet's stated conditions: INA181's 150 µV at 25°C/0 V common mode gives 0.3 A, while 500 µV at 12 V gives 1 A; INA241A3's 10 µV at its default 48 V condition gives 20 mA. This is not an equal-condition system-performance comparison, but shows why low-current detection cannot rely on full-scale gain error alone. More gain reduces ADC-referred error, not VOS/Rsh. A larger shunt reduces that term but increases drop and I²R loss.

6. A PWM sampling window is not simply the inverse of bandwidth

INA241A enhanced PWM rejection reduces output disturbance from large common-mode edges; it does not establish valid current at every instant. Rev D section 7.3.1.1 describes an approximately 1 µs output hold after a large common-mode transition, with bandwidth and AC CMRR attenuating another edge in the following 3 µs. It gives enhanced-rejection conditions up to 125 kHz PWM or at least 3 µs between common-mode edges. At extreme duty cycles, check edge spacing rather than only PWM fundamental frequency.

The typical 1.1 MHz small-signal bandwidth, fixed-common-mode step settling and PWM common-mode recovery are different tests. Combine the invalid interval after switching, external-RC settling, ADC acquisition and trigger jitter into a sampling window, then verify that current at that instant represents the control objective. Excess output RC can reduce noise while delaying protection; mismatched input resistors can introduce additional errors through bias currents and the gain network.

Use Kelvin shunt sensing to keep high-current copper drop out of the millivolt signal, and avoid shared switching-current impedance in reference and ADC returns. Bench tests should sweep common mode at zero current, vary PWM duty/edges at fixed current, apply positive/negative current steps and repeat after heating. Derive the usable sampling window from these measurements rather than treating typical plots as guarantees for every board.

7. Make the error budget a traceable acceptance record

Maintain included and pending-verification columns in the budget, binding every limit to datasheet revision, gain, common mode, supply, temperature and output conditions. This checklist supports engineering review; it is neither a metrology certificate nor a functional-safety argument.

• Define the sensing node, positive/negative current range, both input pins' common-mode/transient envelope and isolation needs; treat AMC3330 as a voltage-input device.
• Freeze gain and OPN: INA181 350 kHz is A1 only; check INA241A offset, gain and drift by version without inheriting B3 Grade 0.
• Build the shunt thermal model from initial tolerance, TCR, power/pulse ratings and Kelvin layout, separating resistor and amplifier temperatures.
• Check both range endpoints, zero-current output and overload against amplifier accuracy range, ADC range and power-sequencing protection.
• List offset, gain, shunt, ADC quantization/gain/offset, reference, CMRR/PSRR, filters, noise and dynamic residuals in amperes; do not call a subtotal total accuracy.
• Bind calibration to temperature, common mode, reference and current standard; test zero, both full scales and low current, including coefficient persistence and failure detection.
• Find a valid sampling window at the target PWM edges, duty cycle, load and ADC trigger; repeat hot tests and check protection latency.

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