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[News] Intel Reportedly Touts 90%+ Wafer Utilization with Interposer-Free EMIB, Eyes 70+ Bridges per Future AI Chip

What happened

According to ZDNet Korea, with TSMC's CoWoS capacity running tight, Intel is spotlighting its advanced packaging technologies EMIB (Embedded Multi-die Interconnect Bridge) and EMIB-T as an alternative. Kyu-oh Lee, Intel's Director of Foundry Packaging, said EMIB uses small, localized silicon bridges instead of a full-size interposer, achieving silicon wafer utilization of over 90%, versus roughly 60% for interposer-based designs. The report notes EMIB-T, which integrates TSVs into the bridges to enable power delivery, has drawn positive industry attention and is reportedly gaining traction among major U.S. tech firms: Google's TPU v9 lineup could reportedly adopt Intel's EMIB-T for both HumuFish and TriggerFish, while WhaleFish is expected to use TSMC's CoWoS-L; Amazon is also reportedly planning to incorporate EMIB-T into its custom AI chips, according to ZDNet. According to Lee, AI chips commercialized in 2026 feature packages measuring up to 120 × 120 mm, integrating 12 HBM stacks and more than 20 EMIB bridges; AI chips currently under development are targeting packages of at least 120 × 180 mm, with 16 or more HBM stacks and at least 38 bridges; and Intel envisions 240 × 240 mm packages integrating over 32 HBM stacks and more than 70 EMIB bridges. As previously reported by the Economic Daily News, UMC manufactures EMIB silicon bridges using mature 12-inch wafer processes at its fabs in Taiwan and Singapore. Meanwhile, according to TrendForce, TSMC's CoWoS-L is expected to support a 5.5X reticle-size package integrating four chiplets and 12 HBM stacks in 2026, and is projected to scale to 14X by 2028, accommodating 20 chiplets and 20 HBM stacks. The potential customer adoptions are reported plans/expectations, not confirmed implementations. The source does not state the cause.