Beth Keser, SEMI's vice president of technology coalitions, now forecasts that glass substrates will enter the market around 2028, two years earlier than her previous forecast of around 2030. She said the rapid expansion of AI and data center chip package sizes is accelerating the adoption of glass substrates, as package dimensions are growing too quickly for the industry to wait until around 2030. This is an industry forecast, not an achieved market entry.
Topco Scientific (TSC) is evaluating a new base in Boise, Idaho, and plans to strengthen its local technology, engineering, and supply chain capabilities to pursue memory and advanced-process opportunities. The company already operates service bases in Phoenix, Arizona, and Dallas, Texas. The source links this plan to the US entering a fresh wave of chip manufacturing expansion and Micron ramping up advanced memory investment. The event remains at the evaluation/planning stage and is not a confirmed implementation outcome.
After posting record-high net profit in the third quarter, TSMC management projects 4Q26 revenue to land between US$52.3 billion and US$54.3 billion, representing a year-over-year increase of approximately 58% and a sequential gain of around 14%. Based on an assumed exchange rate of NT$31.8 per U.S. dollar, TSMC forecasts a gross margin of 65%–67% and an operating margin of 56.5%–56.8%, with the rapid expansion of 2nm production weighing on margins. Despite the near-term margin pressure, CEO C.C. Wei struck an upbeat tone on demand for leading-edge technologies, and TSMC now expects full-year 2026 revenue to grow approximately 44% in U.S. dollar terms, up from its previous outlook of around 40%. TSMC reiterated its 2026 capital expenditure guidance of US$60 billion–US$64 billion and reaffirmed plans to spend significantly more over 2026–2028 than in the preceding three years, underscoring its commitment to expanding capacity for long-term demand, fueled by AI including emerging agentic AI applications. In the third quarter, 2nm's share of wafer revenue climbed to 8% from 3% in 2Q26, 3nm accounted for 33%, 5nm 28% and 7nm 10%, with advanced nodes (7nm and below) contributing 79% of total wafer revenue; HPC platform revenue surged 22% sequentially to 68% of third-quarter revenue, smartphones 21%, and automotive and IoT 4% each.
According to Reuters, citing sources, SK hynix is reportedly seeking U.S. approval to expand chip production in China via its U.S. subsidiary Solidigm, which aims to install additional equipment in unused space at the NAND flash facility in Dalian, China — specifically Mod B, a fabrication space completed in 2023 whose equipment installation was left unfinished due to the memory market downturn — as a condition for investing in a U.S. facility, with the expanded operations helping fund a new NAND manufacturing plant in the U.S.; Solidigm is also reportedly considering an initial public offering as early as next year to raise additional capital. However, SK hynix told Reuters that equipment installation at Dalian's Mod B facility is proceeding in consultation with and under authorization from the U.S. government, and that it is not seeking to expand capacity at Mod B; Solidigm declined to comment. As background: in September 2025, the U.S. Commerce Department revoked special authorizations that had allowed SK hynix and Samsung to receive U.S. chipmaking equipment at their Chinese facilities without individual export licenses, saying it would continue allowing shipments needed to maintain existing operations but did not intend to approve exports for capacity expansion or technology upgrades; in December 2025, Washington granted annual approval for U.S. chipmaking equipment shipments to Samsung and SK hynix's Chinese facilities for 2026, per Yonhap News, though Reuters reports the authorization for the Dalian plant limits equipment quantities and approval for additional U.S.-made equipment and technology in 2027 has yet to be issued. Per The Bell, access to advanced etching equipment is particularly important as NAND makers increase stacked layers, and using older tools can require additional processing steps, reducing productivity and raising manufacturing costs; per Reuters, the Dalian NAND facility uses equipment from major U.S. suppliers including Lam Research, Applied Materials, and KLA.
NAND flashSK hynix, Solidigm and 3 totalTrendForcePolicy/Regulation
On October 14, 2026, TDK Corporation (TSE:6762) announced worldwide distribution availability of its InvenSense PositionSense, a two-chip nine-axis sensor solution that integrates TDK's lowest-power 6-axis SmartMotion IMU, a 3-axis magnetometer based on tunnel magneto resistance (TMR) technology, and on-chip sensor fusion and calibration software, targeting positioning accuracy and navigation for wearables, robotics, drones, mobile devices, and other Physical AI applications. The solution is offered in four hardware configurations: ICM-45608 + ICT-15318 (I2C/SPI/I3C support at 1.8V VDDIO, 16g/2000dps Accel/Gyro full-scale range); ICM-45608 + ICT-15312 (I2C/SPI support at 1.2V VDDIO, 16g/2000dps); ICM-45689 + ICT-15318 (extended ±4000 dps gyroscope and ±32 g accelerometer full-scale range, I2C/SPI/I3C at 1.8V VDDIO); and ICM-45689 + ICT-15312 (±4000 dps/±32 g, I2C/SPI at 1.2V VDDIO). This is a product availability announcement; the source does not state the cause.
IBM (NYSE: IBM), in collaboration with Siemens, today announced new research aimed at advancing IBM's nanostack architecture, a new transistor architecture IBM unveiled earlier this year. The collaboration will combine IBM's leadership in semiconductor device innovation with Siemens' expertise in electronic design automation (EDA), process simulation, lithography optimization, and advanced manufacturing software to accelerate the development of nanostack. According to the source, nanostack is the industry's first known three-dimensional, nanosheet-based design, vertically stacking and staggering transistors to pack more transistors onto a chip, with nearly 100 billion transistors in a space the size of a fingernail at its current 7 angstrom node. The design also unlocks the use of different material combinations within each stacked layer to optimize each transistor's performance and power efficiency independently, powering leaps in energy efficiency, performance, and SRAM scaling. This is an announced research collaboration, in the planning stage; the source does not state the cause.
SK hynix has detailed plans for an in-house core named a Hynix Transaction Processing Unit (H-TPU), intended to reduce reliance on power-hungry CPU cores. The plan was presented by Koo In-jae, the company's VP of SoC design, at ISOCC 2026 (the International SoC Design Conference), and remains a plan rather than a shipping product: H-TPU has yet to be proven in an actual enterprise SSD controller product, and no date has been given. The H-TPU uses a four-stage, in-order pipeline, is placed in clusters to handle repetitive tasks such as read/write command processing, metadata management and buffer control, with more than 100 H-TPUs in total; management remains with the traditional Arm CPU, making it an offload rather than a replacement. The cores are claimed to draw only about 2.5% of a general-purpose CPU core's power, with around 4% of its area (the CPU core used for comparison is not named). The reported cause is that SSD controller CPUs are at their limit on power and area, and PCIe bandwidth doubles every generation while controller CPU clocks and control capability reportedly cannot keep up. SK hynix reportedly plans to apply H-TPU across its NAND products, including next-gen enterprise SSD controllers, and to high-bandwidth flash (HBF), which the outlet said is due next year; the H-TPU is reportedly already being used in 'Storage Next', Nvidia's name for the joint AIN P project with SK hynix.
TDK introduces the Micronas HAR 3025 dual-die stray-field robust motor position sensor with redundant design, ASIL D ready (SEooC) per ISO 26262:2018 and stray-field compensation per ISO 11452-8:2015; samples are available now and start of production is planned for the first half of 2027. The source does not state the cause.
Siemens announced Tessent™ Silicon Executable (TSE) software, a standalone application designed to translate test patterns and apply them directly onto high-speed interfaces and protocols (PCIe and USB per the title), seamlessly delivering test data from the test equipment ecosystem to the Tessent In-System Test on-chip hardware. This is a product launch announced by Siemens with an ecosystem/collaboration character: TSE launches in collaboration with automated test equipment (ATE) providers Advantest and Teradyne. Advantest stated it is integrating Siemens TSE into its V93000 platform with Link Scale and extending it into pre-silicon verification and DFT lab engineering with SiConic; Teradyne stated it has integrated Tessent Silicon Executable into its UltraPort instrument for UltraFLEXplus and claims to be the first tester company to give customers a standard path to run SSN over PCIe for PCIe Gen 6 interfaces, which it says dramatically improves performance and reduces test times. Ankur Gupta of Siemens EDA cited silicon complexity, multi-die and new transistor technology driving growth in test content as the driver. The source provides no quantitative price or market-impact data.
Tessent Silicon Executable (TSE) softwareTessent In-System Test on-chip hardwareSiemens, Advantest and 3 totalEE JournalPartnership/M&A
Rambus launches a new PMIC designed for LPDDR6 SOCAMM2 modules to enhance power efficiency in AI infrastructure. This technical advancement supports the growing demand for low-power, high-performance server memory solutions.
Intel and Micron Technology urged Taiwanese semiconductor materials, components and equipment suppliers to establish operations in the United States, speaking at the SEMICON West 2026 Taiwan Supply Chain Forum in San Francisco on Oct. 12. Ben Fulmer, vice president of construction and sourcing at Intel Foundry, encouraged Taiwanese companies to invest locally so they are ready when selected as a supplier. Shane Smith, senior director of front-end materials strategic sourcing and supply assurance at Micron, said cooperation with Taiwanese suppliers had enabled the company to relocate a significant portion of its DRAM business to the US, noted that transporting all the equipment and materials is a challenge, and emphasized that investment in the US was necessary to develop the ecosystem. Both companies are expanding US manufacturing: Intel is investing more than $100 billion across Arizona, New Mexico, Oregon and Ohio, while Micron plans to invest more than $250 billion by 2035. The forum was organized to connect Taiwanese suppliers with US manufacturers, academic institutions and government agencies; Intel and Micron delivered keynote addresses. Participating Taiwanese companies included Topco Scientific, Challentech International, Gallant Micro Machining, United Integrated Services and Yesiang Enterprise. The urging is an appeal, not a confirmed investment commitment.
BOE Chairman Chen Yanshun visited South Korea on Oct. 12 and met with Samsung Electronics CEO TM Roh. Industry officials believe the two executives discussed supplies of liquid crystal display (LCD) panels for TVs and organic light-emitting diode (OLED) panels for smartphones. LCD supply volumes and pricing are key issues: Samsung Electronics has become increasingly dependent on Chinese panel makers since South Korean manufacturers stopped producing TV LCD panels, and its largest supplier is China Star Optoelectronics Technology (CSOT), a subsidiary of TCL. Samsung has reportedly been sharply increasing purchases from BOE this year to reduce its reliance on any single supplier, and negotiations over purchase prices amid fluctuations in LCD panel prices are another issue. The potential resumption of OLED transactions for smartphones is also drawing attention: Samsung Electronics began sourcing some OLED panels for its Galaxy A57 from CSOT this year; BOE previously supplied OLED panels for Samsung's Galaxy A and M series, but shipments stopped amid a patent dispute with Samsung Display, a Samsung Electronics subsidiary, and a settlement reached last November cleared the way for business to resume. The meeting came about four months after Roh visited BOE in China in June; Chen also traveled to South Korea last December to meet Samsung Electronics executives, and senior executives from the two companies have met three times in less than a year. Chen is scheduled to visit BOE Korea's recently relocated office on Oct. 14 before returning to China.
LCD panels for TVsOLED panels for smartphonesBOE, Samsung Electronics and 4 totalThe Elec
Related manufacturers
BOE, Samsung Electronics, China Star Optoelectronics Technology (CSOT), Samsung Display
Tata Group's semiconductor fab in Gujarat faces pressure from controlling shareholders demanding quicker returns on the capital-intensive project. This scrutiny casts a shadow over India's ambitious chipmaking plans. Watch for potential delays or cancellations affecting future supply capacity.
Hua Hong Group signed strategic agreements with four Chinese semiconductor equipment suppliers at the inaugural 2026 China Integrated Circuit Exhibition (China Chip Exhibition) in Shanghai, strengthening cooperation on domestic manufacturing technologies. The event also showcased advances in chipmaking equipment, AI accelerators, and electronic design automation (EDA).
semiconductor equipmentAI acceleratorselectronic design automation (EDA)Hua Hong GroupDigiTimes AsiaPartnership/M&A
TOK Inc. completed a new facility at its Koriyama plant to expand photoresist production capacity, driven by rising AI chip demand. This expansion aims to strengthen the company's global market position. The move signals increased supply to meet high demand, which could mitigate current shortages.
King Yuan Electronics (KYEC) has signed a prepayment agreement with Nvidia to support its wholly owned US subsidiary, AeternZ, in building local testing capacity, giving Nvidia early access to AI chip testing capacity in the US. The move further clarifies KYEC's plans to invest in the US, with Fort Worth, Texas, reportedly emerging as the likely site of its operations in the country. The event remains at the agreement/plan stage and the capacity is not yet built.
AI chip testing capacityKYEC, Nvidia and 3 totalDigiTimes AsiaCapacity Change
In an SK hynix Newsroom article series [Inside the Research] Part 2 dated October 14, 2026, the company detailed its research paper "Co-Optimizing Cell, Non-Cell, and Page Schemes for Energy Efficient Analog Computing in 3D FeNAND," published in the 2025 IEEE International Electron Devices Meeting (IEDM), authored by Won-Tae Koo and Jihun Kim of SK hynix's Global RTC. The research proposes a 3D FeNAND-based analog compute-in-memory (A-CiM) architecture that merges storage and computation, and by co-optimizing cell, non-cell (interconnect/word line), and page schemes, achieves approximately 10 to 20 times higher throughput and around 4,000 to 5,000 times greater energy efficiency than conventional 3D arrays under the same chip-area constraints; the article notes these figures reflect 3D FeNAND's high-density advantage over conventional 2D nonvolatile memory arrays widely studied as A-CiM candidates. Reported optimization results include: using a low-resistance word line metal improved throughput by up to 16% and energy efficiency by up to 3%; air gaps reduced word-line parasitic capacitance by approximately 60%, improving throughput by 1.2 times and energy efficiency by two times; jointly optimizing word line resistance and capacitance improved throughput by up to 1.4 times and energy efficiency by up to 2.2 times; in-page pipelining (IPP) doubled energy efficiency and improved throughput by nine times versus the baseline; and splitting a conventional 16KB page into four 4KB subpages improved energy efficiency by 1.2 times and throughput by 1.7 times. The team also demonstrated four-level-per-cell operation in the low-current region with stable data retention at the 300mm wafer scale. The article states the research shows NAND's potential to expand beyond a storage medium into a computing medium; the source contains no price, shipment, capacity, or market-condition information.
Automakers are exploring modular AI architectures to reduce computing costs for advanced driver assistance systems (ADAS). According to the source, rising chip costs and growing computing demands are driving automakers toward specialized AI architectures for more affordable, scalable driver assistance systems. This is a background technology-trend item that does not mention specific companies, part numbers, price data or dates.
On its earnings call, ASML warned that even with a planned 30% capacity increase in 2027 followed by another targeted 30% expansion in 2028, its planned capacity would fall short of customer demand in both 2027 and 2028; Reuters, citing CEO Christophe Fouquet, notes that orders for 2028 are already pouring in, with some customers looking to secure equipment as far ahead as 2029 or even 2030. ASML expects to ship around 65 systems, up more than 50% from last year, and the outlook for DUV immersion tools has improved significantly: after initially anticipating a decline in shipments, the company now expects volumes to remain roughly flat year over year. ASML confirmed it will introduce the NXE:3800F EUV scanner in 2027, boosting wafer throughput from today's 230 wafers per hour to 260 wph, a breakthrough the company said is expected to meaningfully scale customer production capacities starting in 2028 and beyond; it is also upgrading key DUV immersion tools scheduled for delivery in 2027 to a record 330 wph. On pricing, ASML said pricing discussions with major customers have concluded, with the impact expected to be minimal in 2026, beginning in 2027 and fully visible from 2028 onward; according to The Elec, ASML is reportedly seeking a 10% price hike on replacement parts supplied to South Korea, with Samsung Electronics and SK hynix already notified. Financially, ASML posted record third-quarter net sales of €11.66 billion, up from €9.33 billion in the previous quarter; net profit surged to €4.96 billion from €2.92 billion and gross margin expanded to 57.5% from 54%. It forecasts Q4 revenue of €14.2 billion–€15.2 billion ($15.9 billion–$17.0 billion) with gross margin around 57%, and raised the lower end of full-year revenue guidance by €1 billion to €44 billion–€45 billion while maintaining the upper end, with gross margin of approximately 56%. The price impact has not yet taken effect and the capacity expansions remain planned.
Google DeepMind and Columbia University collaborate to automate chip design verification using AI agents. This addresses the manual bottlenecks in verifying multi-billion-transistor systems. Neutral: Long-term efficiency gain for EDA, no immediate price impact.
EDA ToolsChip DesignGoogle (DeepMind), Columbia UniversitySemiconductor EngineeringTechnical