Nvidia launched RTX Spark AI laptops in Korea, with sales starting Oct. 16; the least expensive model, MSI Prestige N16, is priced at 5.799 million won, and Nvidia attributed the high price to rising memory costs.
Japanese semiconductor company Renesas is accelerating its expansion into the physical AI market, having recently established a dedicated physical AI team within its user experience (UX) organization to provide semiconductors and solutions needed for humanoid robot development. Renesas director Yang Tae-young made the remarks at the "Semiconductors Powering Humanoids" conference held alongside the Semiconductor Exhibition (SEDEX) at COEX in Seoul on Oct. 16. Renesas established its UX organization in the second half of 2024; the global organization covers all markets including Japan, consists of three teams responsible for physical AI, marketing and technology strategy, and has 403 employees, including more than 108 in the physical AI team. The physical AI team provides comprehensive robotics development services, including engineering support and system architecture implementation, with offerings covering microcontrollers (MCUs), microprocessors (MPUs), motor control semiconductors and sensors. Renesas has established a laboratory in Beijing, China, to jointly develop solutions with local humanoid companies and develop its own technologies. Its development tools include MPUs equipped with two 64-bit cores, which can be used in autonomous mobile robots (AMRs). Renesas is also expanding its semiconductor portfolio for robotics, supplying both products for controlling robotic joint motors and industrial network communication devices; humanoids account for 8% of revenue from these products, with the share more than doubling annually, and demand is particularly strong in China. The company is also reducing semiconductor package sizes for humanoid applications, and some robotic joints use dual MCUs to maintain safe operation in the event of a malfunction.
At the "Semiconductors Powering Humanoids" conference held at COEX in Samseong-dong, Seoul, on Oct. 16, Intel vice president Cho Min-sung said the company plans to launch Razor Lake AX, a new SoC designed for robotics applications, in 2028, targeting performance of around 700 TOPS. Intel's current Panther Lake-based robotics development tools theoretically deliver 180 TOPS, and the next-generation Nova Lake is planned for introduction early next year. The article notes that Nvidia's Jetson AGX Orin, an SoC designed for robotics, delivers approximately 275 TOPS. Cho said domestic customers are planning to begin mass production of autonomous mobile robots (AMRs) next year, while most are targeting 2028 for humanoids, which also explains the planned 2028 launch of Razor Lake AX. Intel aims to support deployment of complete robotic systems through its Core Ultra Series 3 robotics computing platform, which integrates a CPU, NPU and GPU and can be used across industrial robotic arms, AMRs and humanoids; Intel also provides the Robinson Bay development platform and software tools including OpenVINO, Physical AI Studio and Robotics AI Suite. These launches remain plans and have not been implemented.
According to Zeng Yi Wong, assistant managing director for manufacturing at Enterprise Singapore (EnterpriseSG), Singapore is targeting high-value semiconductor manufacturing, advanced packaging, and silicon photonics, building on its strengths in engineering, precision manufacturing, and reliability. This is background strategic-positioning information; no specific prices, capacity figures, or company events are stated.
high-value semiconductor manufacturingadvanced packagingsilicon photonicsDigiTimes Asia
Intel announced that its upcoming Razor Lake-AX platform will feature 700 TOPS of AI compute on die, outperforming the current Panther Lake mobile chips (180 TOPS) by 3.88 times.
As reported by Tom's Hardware on 17 October 2026, after rumors that RTX 5090 production was stopping, Nvidia senior VP Jeff Fisher reportedly said in a purported post-event interview that the card has not been discontinued and will continue to ship. He reportedly stated: "The supply chain (capacity) is indeed somewhat constrained, but NVIDIA is doing everything it can to get the product on the market... production has not been discontinued, and NVIDIA will continue to ship," while noting other variants of the RTX 5090 (chip) exist. Earlier rumors held that, after Nvidia reportedly put the RTX 50 Super series on hold, production of the already-rare RTX 5090 was stopping, likely to use precious silicon manufacturing capacity for more AI accelerators. Retail spot-checks: RTX 5090s on Amazon sell for about $8,500 from third-party sellers; Newegg lists 5090s for about $7,300, likely from Chinese sellers judging by shipping time, with U.S. tariffs likely adding to the price; Best Buy has zero cards on offer; and as of this writing the card remains absent from Nvidia's own marketplace and Micro Center. Tom's Hardware received no reply from Nvidia for comment; the claims are reported second-hand, and production status is not officially confirmed.
NVIDIA has responded to and denied reports that the GeForce RTX 5090 is being discontinued. On October 16, after the RTX Spark launch party in Taipei, Jeff Fisher, senior vice president of NVIDIA's personal computing business, told Taiwanese media the rumors aren't true, as reported by 4Gamers and the Central News Agency (CNA). The rumors started last week when leakers claimed NVIDIA had stopped allocating GB202 silicon to the RTX 5090, and BenchLife later said board partners were no longer receiving GB202 chips for the card; the RTX 5090 also seemingly vanished from NVIDIA's own marketplace and from Micro Center shelves. Fisher said the supply chain (capacity) is indeed somewhat constrained, but NVIDIA is going all out to bring products to market; although there are other variants of the RTX 5090 (chip), it has definitely not been discontinued and NVIDIA will continue to ship it. The source does not state the cause of the tight supply. The discontinuation rumor remains unconfirmed, and the event is the denial of a rumor.
On October 17, 2026, Taiwan announced it will add AI servers and the latest chips to its controlled export list to align its policies with U.S. trade bans; the revised Foreign Trade Act will impose penalties of up to five years imprisonment and/or a fine of about $92,500 for smuggling these items once the controls take effect. The move follows a U.S. tariff agreement and a raid on Super Micro, after U.S. authorities accused Super Micro employees of smuggling $2.5 billion worth of AI servers; months later Taiwanese authorities raided Super Micro’s Taipei office, leading to the indictment of nine individuals. Taiwan currently does not treat AI chip exports to China as a crime, and the new controls are not yet in effect.
Japan's Ministry of Economy, Trade and Industry (METI) on Oct. 16 approved a revised plan from Taiwan Semiconductor Manufacturing Co. (TSMC) to build 3-nanometer logic chips at its second fab in Kumamoto Prefecture, on the southern island of Kyushu. 3nm is one of the most advanced chip processes in commercial production. The plan replaces the 6nm and 12nm production approved in February 2024. The source does not state production timing or output details.
Taiwan Mask Corporation (TMC) is acquiring semiconductor equipment services provider TCK for US$4.75 million to target Japan's Kyushu chip expansion, expanding its presence in Japan's Kyushu semiconductor market and extending its business beyond precision photomask manufacturing to equipment assembly and engineering support.
SEMI President and CEO Ajit Manocha told DIGITIMES in an exclusive interview at SEMICON West 2026 that the semiconductor industry reached the US$1 trillion revenue milestone several years earlier than originally forecast, and that with growth driven by AI and quantum computing, reaching US$2 trillion by 2035 is 'entirely achievable'. The headline further states that the SEMI CEO sees a US$3 trillion chip industry by 2035, as trusted partners reshape the supply chain. These are industry-scale forecasts, not achieved results; the source does not state any specific component price or supply change.
Chinese startup Langdao Silex has demonstrated the development of the first homegrown extreme ultraviolet lithography (EUV) laser source, gradually paving the way for China's complete supply chain independence. The system, named FlintNano LPP-OXXO, reportedly delivers over 15 W of EUV output and uses components that are approximately 90% domestically sourced or developed. It relies on laser-produced plasma (LPP), a technique using high-powered lasers to generate plasma and produce the EUV radiation required for advanced chip manufacturing, similar to the process used by ASML. According to specifications published by Langdao Silex, the FlintNano system employs a 1,000 W driving laser operating at repetition rates between 1 and 20 kHz; its conversion efficiency exceeds 2%, and the company claims the equipment can operate continuously for more than 100 hours. The prototype is reportedly suitable for wafer exposure testing, although further finetuning is still necessary. As background, EUV lithography tools are banned from being sold in China after the United States government pressured the Dutch government to halt sales of these advanced tools; ASML has never shipped a single EUV scanner to China, as the Dutch government, under pressure from the United States, blocked exports in 2019, and no system has been deployed, though ASML continues to ship DUV systems to Chinese customers. More importantly, developing a light source is only one part of building a complete EUV scanner, which also requires extremely precise reflective optics, sophisticated wafer positioning mechanisms, and complex integration across numerous subsystems.
According to Tom's Hardware, published 16 October 2026, Chinese startup Langdao Silex (established in 2024 by Tsinghua University's Gas Discharge Plasma Laboratory alumni) demonstrated a prototype EUV light source with over 15W of output power, 90% domestic components, and decent uptime at the 26th China International Industry Fair in Shanghai, without lighting it up. The FlintNano LPP-OXXO system uses laser-produced plasma (LPP) technology with a 1,000W driving laser operating at 1kHz–20kHz, conversion efficiency exceeding 2%, brightness of 100 W/(mm²·sr), continuous operation of over 100 hours, plasma stability of 3% RMS and EUV output power stability of 5%; however, its output remains insufficient for high-volume chip production, and the company has not disclosed whether the 15W is measured at the plasma or at intermediate focus. Per TrendForce, citing various sources, the company will need another three to five years to commercialize its technology. Langdao is also developing the higher-power FlintMicro-LPP EUV source, which has completed proof-of-principle validation, but its output power, conversion efficiency and operating lifetime are undisclosed. A light source alone does not make an EUV scanner; a complete EUV lithography scanner would require further advances in collection/illumination optics, multilayer mirrors, wafer and reticle stages, and system integration.
Samsung will reportedly break ground on its second chip fab in Taylor, Texas, this November, with mass production targeted for 2030. DigiTimes, citing South Korea's The Guru, reports that Taylor Fab 2 will span roughly 2.7 million square feet. Samsung also appears to have confirmed the timing at an October 15 event near the site, where Jonathan Taylor of Samsung Austin Semiconductor said construction should start early next month and that Fab 2 will be one and a half times bigger than Fab One. The process for Fab 2 has not been disclosed yet. As background, the first Taylor fab has slipped well past its original 2024 target and seems to be on track this time, with installed tools starting to run processes during staged qualification; Fab 1 uses EUV lithography for Samsung's 2 nm process, with operations planned by the end of 2026 and volume production in 2027. Its best-known customer is Tesla, which signed a $16.5 billion deal running through 2033 covering the AI6 chip, and Samsung is also set to build Tesla's AI5 on 2 nm in Texas. How orders will be split between the two fabs is unknown. Samsung plans to invest over $37 billion across Central Texas, backed by up to $4.745 billion in CHIPS Act funding. Given how long Fab 1 took, the source notes it is reasonable to expect the 2030 target will depend heavily on demand.
On the recent investor call, TSMC Chairman and CEO Dr. C.C. Wei said assessed demand exceeds available supply, and the company is responding with new factories, equipment conversions, productivity improvements and flexible manufacturing across technology generations. Third-quarter revenue reached $46.7 billion, and TSMC forecasts approximately 44% revenue growth for 2026 in U.S. dollar terms (a forecast, not an achieved result). Wei described nearly 20 fabrication facilities under development worldwide, including leading-edge manufacturing and advanced packaging projects, and the company expects annual capacity for its N2 technology family to more than double in 2027 (an expectation). Wei said TSMC is expanding 3-nanometer production despite its historical practice of avoiding further expansion once a technology generation reaches its targeted scale. TSMC outlined manufacturing plans in Taiwan, Arizona and Japan, alongside preliminary evaluations in Texas; Wei linked U.S. expansion to customer requests and said manufacturing location can affect pricing. He also acknowledged some shortage in backend packaging capacity, mentioned cooperation with GlobalFoundries, and noted that company teams are examining U.S. data-center construction and electricity availability, since chip deployment depends on functioning infrastructure. Wei also warned that rising component prices and economic uncertainty are challenging consumers and price-sensitive markets.
Terafab’s project has secured $16.8 billion for phase‑one funding (up to $119 billion total across four phases); its research fab in Austin is iterating on process recipes, transistor designs and packaging variants at a few thousand wafers per month, while the volume fab under construction in Grimes County is targeting 100,000 wafer starts per month with first silicon expected in 2029, using Intel’s 14A process as named by Elon Musk. The site and phase‑one funding are approved and the research fab is under construction, but no first‑wafer date or ownership terms have been made public and neither Tesla nor Intel is contractually bound. The article argues that advanced packaging, not lithography, will determine whether the single‑roof concept pays off.
Bare-die shots revealed via the Moore's Law Is Dead YouTube channel have exposed details of Intel's upcoming "Nova Lake" lineup for mobile devices. The "Nova Lake-HX" features an 8+16+4 core configuration with 8 P-Cores, 16 E-Cores, and 4 LPE-Cores, with total silicon measuring 12x30 mm amounting to 360 mm², divided across six dies on various nodes: the graphics tile is built on the Intel 3-E node, embedding 4 Xe GPU cores and covering roughly 26 mm²; a 21 mm² dummy die provides structural integrity of the package; a large 72 mm² die on the Intel 18A-P node hosts 4 LPE-Cores and serves as a central hub; another 18A-P die of 58 mm² functions as a peripheral control tile; the main compute tile is made at an external foundry on the TSMC N2P node and hosts the 8P+16E CPU core configuration, occupying the largest area of 104 mm²; a passive tile of 85 mm² sits beside it for the structural integrity of the package and the intended operation of the "Nova Lake-HX" chip. The less powerful "Nova Lake-H" variant features a 4+8+4 configuration with 4 P-Cores, 8 E-Cores, and 4 LPE-Cores; its package is significantly smaller at 12x23 mm for a total die area of 276 mm². The die configuration remains the same except for the main compute tile, which hosts a 4P+8E-core configuration on the TSMC N2P node occupying 55 mm²; its adjacent passive die is smaller at only 45 mm², while the peripheral control die, central hub die, and graphics tile are all made on Intel nodes and remain the same as in the "HX" variant.
mobile processorsCPU coresGPU coresIntel, TSMCTechPowerUp
Indian solar PV module manufacturer Vikram Solar has secured a 187 MW module supply order from a renewable energy developer for solar projects at three locations across the southern Indian states of Karnataka and Tamil Nadu. Under the agreement, Vikram Solar will supply its high-efficiency N-Type TOPCon G12R modules, featuring glass-to-glass construction and bifacial technology, with power ratings ranging from 615–625 Wp, the company said. The engagement builds on Vikram Solar's existing association with the developer. The article was published on October 16, 2026, and notes that Vikram Solar is headquartered in Kolkata, West Bengal, with a presence across 39 countries, against the backdrop of India scaling up toward its target of 500 GW of non-fossil capacity. The source does not state the order value or a cause.
N-Type TOPCon G12R solar PV modulesVikram SolarEvertiq
Siemens has announced an expanded collaboration with NVIDIA to accelerate computational lithography for next-generation AI chips, delivering up to 12x faster full-chip optical proximity correction (OPC) workloads. The two companies are integrating NVIDIA's cuLitho GPU acceleration library with Siemens' Calibre manufacturing software to tackle one of the biggest bottlenecks in advanced semiconductor manufacturing. The source does not state the cause beyond the technical bottleneck. This is an announcement of an expanded collaboration; its implementation status is as described in the source.
AI server tracking data shows a clear parallel growth trajectory between semiconductor testing interface providers and chip design houses. The source states the cause as the surge in artificial intelligence (AI), high-performance computing (HPC), and custom ASIC developments; as of September 2026, both sectors demonstrated substantial year-over-year revenue gains. The source does not name specific companies or provide specific percentage figures.
semiconductor testing interfaceschip design servicesDigiTimes Asia