South Korean semiconductor equipment maker Hanmi Semiconductor showcased its high-bandwidth memory (HBM) and AI chip packaging equipment at SEDEX 2026, including the TC Bonder 4 for HBM4 production and the Wide TC Bonder, which is scheduled for launch in 2027 (planned, not yet launched per the source). The company also introduced five 2.5D packaging systems designed to accommodate increasingly large AI chip packages.
TC Bonder 4Wide TC Bonder2.5D packaging systemsHanmi SemiconductorDigiTimes Asia
South Korean ASIC design solutions provider ASICLAND showcased its proprietary AxHub AI chip design and verification platform at SEDEX 2026 and stated that it seeks to accelerate custom chip development and strengthen its advanced process and packaging capabilities through its Taiwan R&D center. The company also disclosed that memory controller projects remain its primary revenue source, supporting its planned expansion into AI chip mass production and overseas markets. These expansion and mass-production plans remain intentions/plans and are not achieved results; the source does not state any cause beyond these stated aims.
AxHub AI chip design and verification platformAI chipmemory controllerASICLANDDigiTimes AsiaCapacity Change
Micron is developing a memory architecture for humanoid robots, joining Samsung Electronics and SK Hynix in efforts to serve physical AI systems that must process sensor data while operating within battery power limits. The companies are pursuing both memory designs and storage products for robots and autonomous vehicles. The source provides no timeline, investment size or mass-production schedule; this development is an ongoing/planned R&D effort with no confirmed implementation or shipment status stated.
memory architecture for humanoid robotsmemory designsstorage productsMicron, Samsung Electronics and 3 totalDigiTimes Asia
LED packaging manufacturer Brightek Optoelectronic faces difficulty meeting growing automotive orders due to tight mature-node logic IC supplies; the source attributes the constraint to foundries prioritising higher-margin memory products. Brightek expects its automotive revenue share to rise from around 50% to exceed 60% following the opening of its Nantong plant and higher shipments; its third-quarter 2026 gross margin is projected to recover to 30% (these are projections, not achieved results).
The source states that AI data center investment continues to expand, keeping the global memory market undersupplied in the fourth quarter of 2026. Rising DRAM and NAND Flash contract prices are boosting expectations for Samsung Electronics and SK Hynix in 2027; however, the source also notes that weak consumer demand and long-term agreement (LTA) price caps will limit further price increases.
DRAMNAND FlashSamsung Electronics, SK HynixDigiTimes AsiaPrice Movement
According to a report by the Seoul Economic Daily on October 18, citing industry sources, Samsung Electronics has agreed after an internal review to use TSMC's 3nm process for the base die of NVHBM, Nvidia's next-generation custom HBM. The newspaper said it would be the first time the two companies have worked together at the HBM manufacturing stage. The report states that Nvidia's custom memory design is shifting control of how HBM is built from memory makers to its largest customer, steering part of that work to TSMC. This is a media report citing industry sources; actual implementation remains to be confirmed.
HBMNVHBMbase dieSamsung Electronics, TSMC and 3 totalDigiTimes AsiaPartnership/M&A
Memory prices are reportedly so high, rising by up to RMB 500 per unit. According to a TrendForce repost, some Chinese phone makers are responding by turning to memory chips salvaged from discarded phones via Shenzhen's Huaqiangbei. The source does not state the cause of the price increase.
memoryTrendForce Official (Market Data)Price Movement
Micron is developing edge inference memory (EIM) for physical AI applications, which stacks low-power DRAM atop a logic die to improve data processing efficiency, with mass production expected in the second half of 2028.
Researchers at UC Berkeley, Samsung Electronics, and Intel published a research paper titled “Nanoelectromechanically Gated Gain Cell eDRAM.” An abstract excerpt states that the memory wall and the slowdown of static random access memory (SRAM) scaling have renewed interest in gain-cell embedded dynamic random access memory (DRAM); while gain cells offer high density and energy efficiency, they suffer from limited retention. This is a research publication treated as background information; the source does not mention prices, capacity changes, or commercialization arrangements.
gain-cell embedded DRAM (eDRAM)SRAMSamsung Electronics, IntelSemiconductor Engineering
According to a Wccftech interview with NVIDIA's Vera team reported on 2026-10-19, NVIDIA has chosen a monolithic compute die for its Vera CPU over the chiplet architectures used by major x86 competitors; Vera also features a custom LPDDR5X memory subsystem and NVIDIA's second-generation Scalable Coherent Fabric. As the report explains, unlike traditional cloud workloads that prioritize high core counts and throughput, agentic AI requires strong single-threaded performance, high memory bandwidth, and low latency to execute sequential tasks quickly and keep GPUs highly utilized. The monolithic design allows CPU cores to communicate without crossing boundaries between separate chiplets, reducing data movement latency. NVIDIA says Vera delivers 3.4 TB/s of bisection bandwidth, three times that of the leading x86 processor used in its comparison; Vera delivers 1.5 times the performance of its predecessor, Grace; and for agentic workloads involving sequential tasks such as Python scripting and code compilation, the company claims up to twice the performance of leading x86 processors, with a 1.6-times advantage on a geometric-mean basis. Vera also introduces NVIDIA's Spatial Multithreading technology. NVIDIA initially positioned its Grace CPU primarily as a host processor for GPU systems, but the report states that growing demand for agentic AI and reinforcement learning has prompted a shift toward standalone Vera CPU racks. Separately, according to the Central News Agency, NVIDIA Senior Vice President of Personal Computing Jeff Fisher denied during an interview in Taiwan rumors that NVIDIA plans to discontinue its flagship GeForce RTX 5090 graphics card, calling them untrue and stressing that the RTX 5090 remains a key product that NVIDIA will continue to supply; he acknowledged supply constraints are affecting the global industry, not just NVIDIA, but said the company is doing everything possible to bring products to market. TechPowerUp adds that the RTX 5090 remains difficult to find near its US$1,999 MSRP, with some listings on Amazon and Newegg exceeding US$8,000.
An Nvidia executive said shortages of consumer graphics processing units (GPUs) stem from insufficient memory supplies, which the company said it cannot control. Nvidia’s flagship consumer GPU, the RTX 5090, is trading for as much as 15 million won or more, roughly five times its tax-inclusive suggested retail price. RTX Spark-based laptops start at approximately 4.7 million won, with prices reaching as much as 10 million won depending on specifications. The company attributed the high prices to rising memory costs. These remarks were made at an RTX Spark launch event in Seoul’s Samseong-dong district on Oct. 16.
According to Seoul Economic Daily (with ZDNet having reported in September that Samsung is pursuing a dual-track strategy for custom HBM, tapping both its own foundry and rival TSMC), NVIDIA has asked Samsung, SK hynix and Micron to adopt TSMC's 3nm process for the base dies of its NVHBM, unveiled in August. Samsung's Device Solutions (DS) division reportedly agreed to the requirements following an internal review. The stated causes are NVIDIA's push to standardize production across suppliers to ensure consistent HBM performance and simplify product validation; additionally, industry estimates place TSMC's 3nm yields above 90%, versus around 60% for Samsung Foundry's 2nm (SF2) process. NVHBM's custom base die integrates the memory controller traditionally housed in the GPU; according to NVIDIA, the technology offers up to 30% more memory bandwidth, 15% lower HBM power consumption and 25% more XPU compute die area than standard HBM4E. The partnership is not entirely new: according to Seoul Economic Daily, Samsung and TSMC first collaborated four years ago to ensure HBM compatibility with TSMC's GPU packaging process, and this latest tie-up extends into HBM manufacturing for the first time. Samsung is keeping its own foundry in play: with TSMC's 3nm capacity facing competing demand from AI accelerators and smartphone chips, Samsung is validating NVHBM base die production on its 2nm process as a potential alternative should TSMC face capacity constraints. TSMC flagged tight 3nm capacity at its October 15 earnings call, with the node accounting for 33% of third-quarter wafer sales, its largest share among all process nodes; according to Economic Daily News, Chairman and CEO C.C. Wei announced plans for another 3nm fab in Tainan, on top of existing expansion projects in Arizona, Japan's Kumamoto and Taiwan's Southern Taiwan Science Park, with the additional fab slated to begin mass production in the first half of 2028. Samsung also continues in-house base die production for its standard HBM lineup: HBM4, which entered mass production earlier this year, and HBM4E, now undergoing production validation, both use Samsung Foundry's 4nm process for base dies, while their core dies are manufactured on 1c DRAM lines at its Hwaseong and Pyeongtaek campuses; Samsung plans to maintain its turnkey approach to base die production for custom HBM supplied to other customers, including AMD.
NVHBMNVHBM base dieHBM4NVIDIA, TSMC and 5 totalTrendForcePartnership/M&A
Huawei scientist Huang Yu said at the October 15, 2026 Bay Area Chip Expo that EDA tools pose the biggest challenge to the Tau (τ) Scaling Law. Huawei formally introduced the Tau Scaling Law on May 25, 2026 at ISCAS 2026, and in October 2026 launched the Mate 90 series featuring the Kirin 9050 Pro chip based on LogicFolding technology, marking the theory's transition from concept to commercial product.
Rising memory prices and tightening supply are reportedly pushing some Chinese smartphone makers to turn to salvaged memory chips. According to TechNews, some brands are said to be sourcing memory chips recovered from discarded phones, potentially including used iPhones, through traders in Shenzhen's Huaqiangbei electronics market. Sources say memory procurement costs have surged, with some chips reportedly costing up to RMB 500 more per unit; the Shenzhen local government is also rumored to be offering smartphone brands subsidies of around RMB 300 per unit, leaving manufacturers to absorb roughly RMB 200. Unable to fully pass on the increases, some brands are reportedly cutting production and sales volumes to limit losses. TechNews notes the reported price increases, subsidies, and use of salvaged chips have yet to be confirmed by Chinese authorities or the companies involved, and such chips are largely limited to ultra-low-cost, unbranded smartphones and are unlikely to enter flagship supply chains. As background: TrendForce says AI server demand continues to squeeze DRAM supply, with shortages and price increases expected to persist into 2027; TrendForce projected global smartphone production would fall 14% year over year to approximately 1.07 billion units in 2026, a forecast revised upward due to earlier-than-expected purchases and restored production. Caijing's April investigation found a Shandong recycler purchased around 1,000 discarded phones in March and dismantled more than 600 for potential chip resale, with some nonfunctional devices reportedly fetching more than RMB 100 each; some recyclers preferred Android phones from OPPO, vivo, and Huawei, while sources told TechNews that Huaqiangbei traders primarily purchased used iPhones. A September STAR Market Daily investigation found refurbished chips can serve lower-end applications such as automotive accessories, IoT devices, and overseas refurbished phones, but analysts cautioned that salvaged chips face yield losses and compatibility risks, and recycling premiums could quickly disappear if major chipmakers adjust production.
Kulicke & Soffa reported fiscal Q3 2026 net revenue of $330.4 million, up 123% year-over-year, with gross margin of 47.8% and non-GAAP EPS of $1.20, beating expectations. The company guided to roughly $375 million for Q4 fiscal 2026 ending October 3, 2026, citing strengthening demand across semiconductor, memory, automotive, and industrial markets.
According to Tom's Hardware, published 18 October 2026, a project-by-project audit shared by SemiAnalysis on 17 October 2026 finds that more than 300 local US data center construction moratoriums have had limited impact on planned buildouts: only about 2.3 GW of the roughly 21 GW of data centers in moratorium areas (about three projects) is likely to be delayed, and this figure excludes the Texas Commission on Environmental Quality (TCEQ) pause. The firm forecasts a total of 38 GW of US data center IT capacity coming online in 2027, more than double that of 2026; of that, 22 GW is under vertical construction and the other 16 GW is mostly financed with site work being done. The enacted local moratoriums cover about 20 GW, with only about 1.5 GW of it delayed; New York's pause adds 0.8 GW more. As of September, the firm tracked more than 400 local instruments across 17 states, the enacted ones including a few permanent zoning bans; this summer New York, Texas, Pennsylvania, and Oregon acted within under two months. Reasons given for the limited effect include that moratoriums do not revoke existing approvals, short ones may expire before later projects need approval, litigation or equipment lead times may already set the schedule, and capacity already under construction or fully permitted is out of reach. Texas Gov. Greg Abbott told the TCEQ to issue no permits for data center projects, and law firm Bracewell expects the pause to last until ERCOT finishes its review in mid-December; the TCEQ's compliance report to Abbott's office is due Monday.
Hardware leaker KeplerL2 claimed on NeoGAF that the RAM and NAND flash storage in Sony's next console, the PlayStation 6, alone cost over $680, a figure that excludes the APU, cooling, power supply and the rest of the hardware. He posted it as a reply to a forum member who floated $680 as a possible subsidized retail price. This is not Kepler's first update: in March he put the console's bill of materials at around $760, and by July that estimate had climbed to roughly $960. Current leaks suggest the PS6 uses GDDR7 memory on a 160-bit bus supporting up to 40 GB, with 30 GB considered the more likely configuration; there have also been reports that Sony looked into cutting memory capacity to keep costs down. The source states the cause: AI data centers are soaking up DRAM and NAND supply, which pushes prices up for everyone. Sony has said nothing official about PS6 pricing, and the source advises treating the claims with caution; it adds that if memory prices stay where they are, a PS6 costing significantly more than the PS5 Pro seems likely, and a $1,000 price tag now looks quite possible.
GDDR7 memoryNAND flash storageDRAMSonyTechPowerUpPrice Movement
Nvidia launched RTX Spark AI laptops in Korea, with sales starting Oct. 16; the least expensive model, MSI Prestige N16, is priced at 5.799 million won, and Nvidia attributed the high price to rising memory costs.
Lee Cheol, vice president at Micron, said at the "Semiconductors Powering Humanoids" conference held as part of SEDEX 2026 at COEX in Seoul on Oct. 16 that Micron is preparing edge inference memory (EIM) for physical AI applications and is discussing with major customers the development of products suited to emerging markets including autonomous driving, humanoid robots, AR and VR. EIM is positioned between AI chips and memory to reduce data processing latency and increase bandwidth; it stacks LPDDR on top of a logic die and, unlike PIM, its computing architecture has not been disclosed, and Micron has not disclosed specific performance targets. The company is developing a method of applying EIM to LPDDR6, with industry observers expecting mass production in the second half of 2028. Micron noted that current AI models for robots use around 1 billion to 2 billion parameters, so memory bandwidth requirements are not particularly high, but as more advanced vision-language models (VLMs) emerge, LPDDR alone will become insufficient, requiring a transition to HBM, which Micron expects to eventually be adopted in humanoid robots. Micron expects future high-performance humanoid robots to require approximately 200GB of DRAM and 4TB of storage, compared with 12GB of DRAM and 256GB of storage used in current service robots. The company said it is collaborating with robot manufacturers, chipset companies and hyperscalers from the early design stages.
SEC said on Oct. 16 that it will supply its Semi-Scan Wafer inline X-ray inspection system to a mass-production line operated by a global outsourced semiconductor assembly and test (OSAT) provider, marking the first commercial deployment of the equipment since its development was completed in the first quarter of this year. Initial units are expected to be delivered soon, with supply volumes projected to increase; the equipment is priced at approximately 2 billion won per unit. Semi-Scan Wafer is designed for wafer-level packaging (WLP) production lines and uses nondestructive inspection to detect defects in microbumps and internal bonding structures, and can also be used to inspect HBM stacking processes. SEC said it will use this first commercial order as a foundation to secure additional global customers and plans to develop HBM and advanced packaging inspection equipment into core growth drivers; the company also said it is expanding production lines for the same customer and has completed preparations to increase supply.
Semi-Scan Wafer inline X-ray inspection systemwafer-level packaging (WLP) inspectionHBM stacking process inspectionSEC, global outsourced semiconductor assembly and test (OSAT) providerThe Elec
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SEC, global outsourced semiconductor assembly and test (OSAT) provider