Researchers at Argonne National Laboratory and the University of Illinois Urbana-Champaign published a technical paper titled "Agentic AI for Heterogeneous System Design Across Chip, Scale-Up, and Scale-Out Domains." An abstract excerpt states that the design space of modern AI/HPC systems has expanded rapidly across compute architectures (including GPUs, dataflow processors, and RISC-V accelerators) and memory technologies (including HBM, GDDR, among others). The paper explores agentic AI for heterogeneous system design across chip, scale-up, and scale-out domains. This is a research publication and involves no specific price, capacity, or supply-demand change.
GPUsdataflow processorsRISC-V acceleratorsArgonne National Laboratory, University of Illinois Urbana-ChampaignSemiconductor Engineering
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Argonne National Laboratory, University of Illinois Urbana-Champaign
According to Wccftech, at the 2026 Open Compute Project (OCP) Global Summit, Intel — which is expanding its silicon photonics capabilities as demand for high-bandwidth optical interconnects grows across AI and high-performance computing (HPC) — claimed to be the only high-volume foundry capable of supplying 300mm indium phosphide (InP) silicon photonics at scale to the broader industry; the technology is intended to support next-generation near-package optics (NPO) and co-packaged optics (CPO). The source notes that conventional InP substrates are generally limited to 150mm (6-inch) wafers, with 3-inch and 4-inch formats still widely used, and that InP crystals are brittle, grow slowly, and present defect-control challenges, limiting laser chip output per wafer and slowing capacity expansion; Intel integrates InP-based laser technology into its 300mm silicon photonics manufacturing platform, aiming to improve production efficiency and scalability. Per TrendForce, NVIDIA has begun shipping its Spectrum-X CPO switches to select partners (developed jointly with TSMC using its Compact Universal Photonic Engine (COUPE) technology), Broadcom continues limited shipments of its 51.2 Tb/s Bailly CPO switches, and at OCP 2026 showcased its third-generation Tomahawk 6-Davisson CPO switch with 102.4 Tb/s of switching capacity and 200 Gbps per channel; TSMC plans to begin production of its COUPE-on-substrate solution in 2026, targeting twice the power efficiency and a tenfold reduction in latency compared with board-level pluggable optics. Per ijiwei, Zhongji Innolight has established a dedicated CPO production line and begun small-volume production of 800G CPO optical modules; some customers have placed orders, with shipments potentially beginning in 2027 and broader adoption expected in 2028, and in September 2026 Huawei introduced its NPO-based Ascend 960 supernode for large-scale AI training and inference. TrendForce states that testing remains a key obstacle to CPO mass production: while optical alignment times have fallen to seconds or less, complete testing of a single photonic integrated circuit (PIC) can still take more than 100 seconds, shifting the bottleneck toward testing speed and cost; TrendForce expects 2027 to be a pivotal year for integrating CPO testing systems, with 2028 a critical period for assessing readiness for large-scale production.
Security researcher Quentin Kaiser disclosed two bugs in Broadcom's proprietary Wi-Fi implementation, dubbed "WPSplinter," dating back to at least 2010. The bugs lie in Broadcom's handling of Wi-Fi Protected Setup (WPS): specially crafted WPS messages can corrupt the router's memory, allowing an attacker within Wi-Fi range to run their own code on the device without needing the password. According to Kaiser, Broadcom knew about the vulnerability in 2018 and released a partial fix without public disclosure, subsequently recommending manufacturers switch to the open-source hostapd software. Kaiser demonstrated working exploits against routers supplied by Belgian providers Proximus and Orange — on an ASKEY TCG3000 gateway he ran code and extracted the Wi-Fi password — and also found the flaw in Netgear and Technicolor routers supplied by VOO. He estimates around 850,000 Proximus gateways, 500,000 at VOO and 210,000 at Orange Belgium could be affected, roughly 1.56 million routers in Belgium alone (rough estimates, he admits), with worldwide numbers potentially considerably higher. Routers running older eCos-based chips (BCM3380, BCM3383, BCM33834) may never get a fix — Kaiser calls the flaw a "forever day" — while routers using Linux-based BCM3390, BCM65xx, and BCM68xx chips are also at risk unless manufacturers switch to hostapd. Kaiser first reported the vulnerabilities to Broadcom on July 18 with a second report on July 27 and a 90-day disclosure window; Broadcom responded on July 28 saying a patch was available, then declined to assign a CVE identifier; CERT/CC closed its case on August 4. By October 15, the day before his presentation, Kaiser said none of the affected devices he had identified had received a patch. He has not reported evidence of attacks in the wild. The source does not state any price or supply impact.
According to a leak (attributed to well-known leaker Jaykihn), Intel is preparing to launch its Xeon E-series based on "Nova Lake" silicon in two versions: big P-Core only or efficiency E-Core only SKUs, with no hybrid SKUs containing both P-Cores and E-Cores, as those will be reserved for the regular "Nova Lake-S" desktop processors. The P-Core only lineup reportedly will include five configurations with 4, 6, 8, 12, and 16 P-Cores, while the E-Core lineup will be slightly smaller with four SKUs featuring 4, 8, 16, and 32 E-Cores; at the top of the range, buyers can choose between a 16 P-Core design or a 32 E-Core configuration. The new Xeon E designs will be powered by the W980 chipset platform, supporting native DDR5 memory with ECC, up to 48 PCIe lanes (including 12 PCIe 5.0 lanes and 12 PCIe 4.0 lanes from the chipset), and Intel vPro technology; DMI 5.0 x4 sets the DMI chipset bus bandwidth at 128 Gbps per direction; the CPU offers two 40 Gbps USB4 or Thunderbolt 4 ports; the processor-attached PCIe 5.0 x16 PEG slot can be segmented into x8/x8 or other combinations using lane switches; and both CPU-attached M.2 NVMe slots can be configured as Gen 5. This is leaked, planned product roadmap information; the source does not state the cause, and no price or supply figures are provided.
Lenovo launched the Yoga Pro 9n laptop in South Korea on Oct. 19, powered by Nvidia RTX Spark. The laptop features an SoC combining an Arm-based CPU with an RTX GPU based on Blackwell architecture, supporting up to 128GB of unified memory. Prices start at 6.749 million won for the 64GB LPDDR5X model, with a preorder price of 6.24 million won. It includes Lenovo X Power cooling, TDP up to 80 W, two fans, four copper heat pipes, and operating noise as low as 22 dB. The 15‑inch OLED display offers up to 1,100 nits peak brightness, 165 Hz VRR, and 100% coverage of sRGB and DCI‑P3. The touchpad uses ForcePad for haptic feedback, and the laptop supports the second‑generation Yoga Pen with Wacom AES 3.0. The aluminum chassis has a Comfort Edge design, measures 16.7 mm thick, weighs about 1.65 kg, includes a 92.5 Wh battery, and supports USB4. Additional features are a Dolby Atmos‑certified four‑speaker system, three microphones with 3D noise cancellation, a specialized keyboard coating, concave keycaps, and 1.5 mm key travel.
Sandisk announced on Oct. 19 that it will be the exclusive supplier of flash memory for Meta's virtual reality (VR) glasses, which are scheduled for launch in spring 2027. The products include microSD Express memory cards and USB-C flash drives. Sandisk recently entered into a partnership with Meta to jointly design flash memory products for VR applications, and the products have undergone preliminary testing to meet Meta's quality standards. Sandisk will begin selling the related storage products following the launch of Meta's VR glasses. Sujin Park, vice president of consumer products at Sandisk, said high-performance microSD Express memory cards are compatible with Meta VR glasses, allowing users to instantly expand their available storage. The source does not state any impact on price or supply.
FADU announced on Oct. 19 that it posted record third-quarter revenue of 143.6 billion won and operating profit of 36.3 billion won, up 96% and 124% respectively from the previous quarter; revenue surged 460% year-on-year and operating profit turned positive. As of October, the company secured approximately 456.3 billion won in new orders based on regulatory disclosures, more than four times its 2025 full-year revenue of 92.4 billion won, driven by rising demand for memory used in AI infrastructure among global technology giants and major cloud service providers. FADU has completed development of its next-generation PCI Express Gen6 solid-state drive (SSD) controller and plans to begin full-scale sales by year-end, while developing a Gen7 controller targeting delivery of samples to customers in 2028. At the 2026 Open Compute Project (OCP) Global Summit on Oct. 15, FADU unveiled its File Semantic SSD (FS-SSD) technology for data centers. The company is also expanding its product portfolio beyond power management integrated circuits (PMICs) and power loss protection ICs (PLP ICs) into data signal recovery and high-speed signal solutions.
Shindo Eng Lab, a display bonding equipment maker, unveiled a chip packaging architecture at SEMICON West 2026 in San Francisco on Oct. 15 local time that vertically stacks a graphics processing unit (GPU) and high-bandwidth memory (HBM) with a glass-ceramic interposer approximately 200 micrometers (μm) thick between them. In the proposed structure, the GPU sits above and the HBM below the interposer, and the two chips are connected through vertical conductive vias in the interposer; liquid cooling modules are attached above the GPU and below the HBM to dissipate heat in opposite directions, and power is delivered from a printed circuit board (PCB) at the bottom through metal pillars to the interposer, which distributes it to both chips. According to the source, current AI semiconductor packages use a 2.5D architecture that places GPUs and HBM side by side on a silicon interposer; vertical stacking shortens the distance between chips but creates challenges including concentrated heat and warpage caused by thermal expansion and contraction, and Shindo claims its glass-ceramic interposer, which allows thermal expansion characteristics to be adjusted, combined with cooling on both sides can mitigate these problems. The technology used to form the vertical conductive vias is Through Glass-Ceramic Via (TGCV), which the company unveiled in September; the process uses photolithography to form hole patterns simultaneously in a glass-ceramic substrate before filling them with copper, and Shindo initially introduced TGCV as a potential replacement for organic cores in flip-chip ball grid array (FC-BGA) substrates. Shindo has primarily supplied lamination and vacuum bonding equipment used to attach display panels to cover windows and has no previous experience in the semiconductor substrate business. The company has filed a patent application for the proposed architecture and is holding technical discussions with approximately 10 companies, having provided samples to some of them; it has not disclosed whether it intends to manufacture and sell interposers directly or supply equipment. A Shindo official said the ultimate goal is to implement a 3D architecture that vertically integrates GPUs and HBM using TGCV as the underlying technology, and the company plans to present the structure to outsourced semiconductor assembly and test (OSAT) companies and discuss potential applications. The architecture remains a proposal; no mass production or commercialization is reported.
GPUHBM玻璃陶瓷中介层（glass-ceramic interposer）Shindo Eng LabThe Elec
In a TrendForce post dated October 19, 2026, Micron sees potential for HBM in future humanoids, as increasingly sophisticated AI models drive bandwidth needs beyond what LPDDR can deliver. Micron sees future robots needing 200GB DRAM plus 4TB storage and is developing EIM for physical AI, with production reportedly expected in 2H28. These are forward-looking views and a development plan; the production timing is qualified as 'reportedly' and has not been realized.
HBMLPDDRDRAMMicronTrendForce Official (Market Data)Capacity Change
Technology Industries of Finland (TIF) published its recommendations on the EU Chips Act 2.0 (a Commission proposal still to survive the legislative process, with funding not yet settled), arguing the Act must start with demand. Market context figures cited: global chip sales reached $701bn in 2025, will pass $1trn this year and, by the European Commission's reckoning, reach $1.6trn by 2030; Europe makes less than a tenth of the world's chips and covers about a fifth of its own consumption. Proposal points cited: for the first time the Act tackles demand as well as supply (Grand Challenges, industry-led Demand Accelerators, innovation procurement); first-of-a-kind status now spans the whole value chain; permitting is capped at 12 months; quantum chips and photonics get dedicated support. Funding: the Regulation itself contains almost no new money, to be settled separately in the EU budget for 2028 to 2034 and the European Competitiveness Fund; the Commission's impact assessment models an example investment of €40bn, and industry has suggested a ring-fenced EU semiconductor budget of €30bn to €60bn. The proposal's strategic-project priority list includes advanced manufacturing, AI chips, memory and leading-edge design but leaves out quantum and photonic chip manufacturing. The article also notes Finland's industry-led strategy 'Chips from the North' aims to triple the sector's revenue to between €5bn and €6bn by 2035, and sets out seven recommendations (act at speed; secure EU funding of critical mass from every window of the Competitiveness Fund; keep and extend the first-of-a-kind definition to quantum-chip manufacturing; use strategic projects for demand-led critical capacity anchoring an advanced fab; give industry a structured role; build resilience via trusted partnerships; keep security-of-supply obligations narrow). The source does not state the cause — this is an opinion/analysis piece, not a price movement or discrete event.
semiconductorsMEMS and sensorsphotonicsEvertiqPolicy/Regulation
Tesla CEO Elon Musk has predicted a surge in Chinese memory chip production by 2028, raising questions over Samsung Electronics and SK Hynix's pricing power during an AI-driven dynamic random-access memory (DRAM) shortage. His remarks suggest that China's expanding capacity could offer major technology buyers alternative sources of supply and potentially ease memory costs. This is a prediction, not an implemented capacity change; the source does not state the cause.
DRAMSamsung Electronics, SK HynixDigiTimes AsiaCapacity Change
A technical article published on Semiconductor Engineering discusses breaking the memory bottleneck in AI and HPC SoCs, covering the optimization of embedded memory IP for RibbonFET and PowerVia. The article is technical background content and reports no price movement, capacity change, policy event, or supply-demand data.
Nvidia has asked Samsung, Micron and Hynix to use TSMC 3nm base dies for its custom NVHBM, citing standardisation as the reason; Samsung and Micron have confirmed their agreement, with volume production expected in 2027; Hynix was already using TSMC’s 12nm process for HBM4 base dies; Samsung is also validating base-die production on its own 2nm process as a backup; Samsung will continue to make standard HBM for customers who do not want NVHBM. NVHBM offers up to 30.% more bandwidth and 15% lower power than standard HBM4E.
base dieSamsung, Micron and 3 totalElectronics WeeklyPartnership/M&A
According to Gartner's October 2026 report, Q3 2026 PC shipments totaled 55.4 million units, down 22.4% year-over-year. The increase in memory and storage costs, with DRAM costs up five times YoY in Q2, led PC vendors to pass higher component costs to customers, driving the steep decline in shipments. Shipments have fallen to levels last seen in early 2023, with the decline driven by higher prices, vendor-led reprioritisation of scarce components, and a shift toward higher-priced configurations, reducing availability of lower-cost devices and making replacement less affordable for consumers, while businesses shifted spending to targeted investments such as workstations and AI PCs. All top six worldwide PC vendors saw shipment declines in Q3 2026: Lenovo -22.4%, HP Inc. -30.9%, Dell -25.4%, Apple -7.1%, ASUS -13.0%, Acer -11.2%, Others -25.6%. Apple gained 1.7 percentage points of market share.
DRAMLenovo, HP Inc. and 6 totalElectronics WeeklyPrice Movement
SK Hynix is strengthening its metrology and inspection (MI) capabilities as the transition toward 3D DRAM architectures and increasingly complex NAND stacking creates new challenges for conventional semiconductor inspection technologies. The source does not state specific measures, timelines, or impacts on capacity or pricing.
AI-driven memory demand is growing exponentially, pushing the industry into a structural supply shortage. Per the title, memory giants have locked in up to 70% of capacity under long-term deals. The body states that as supply tightens and contract prices surge in 2026, major AI companies and cloud service providers (CSPs) are increasingly signing long-term agreements (LTAs) lasting three to five years with memory manufacturers to secure supply and manage soaring costs. No specific companies are named in the source.
CXMT expects to report net profit of CNY131 billion to CNY132.5 billion (approximately US$19.58 billion to US$19.8 billion) for the first nine months of 2026, reversing a year‑earlier loss driven by surging AI computing demand that is causing memory chip shortages and higher prices.
South Korean semiconductor equipment maker Hanmi Semiconductor showcased its high-bandwidth memory (HBM) and AI chip packaging equipment at SEDEX 2026, including the TC Bonder 4 for HBM4 production and the Wide TC Bonder, which is scheduled for launch in 2027 (planned, not yet launched per the source). The company also introduced five 2.5D packaging systems designed to accommodate increasingly large AI chip packages.
TC Bonder 4Wide TC Bonder2.5D packaging systemsHanmi SemiconductorDigiTimes Asia
South Korean ASIC design solutions provider ASICLAND showcased its proprietary AxHub AI chip design and verification platform at SEDEX 2026 and stated that it seeks to accelerate custom chip development and strengthen its advanced process and packaging capabilities through its Taiwan R&D center. The company also disclosed that memory controller projects remain its primary revenue source, supporting its planned expansion into AI chip mass production and overseas markets. These expansion and mass-production plans remain intentions/plans and are not achieved results; the source does not state any cause beyond these stated aims.
AxHub AI chip design and verification platformAI chipmemory controllerASICLANDDigiTimes AsiaCapacity Change
Micron is developing a memory architecture for humanoid robots, joining Samsung Electronics and SK Hynix in efforts to serve physical AI systems that must process sensor data while operating within battery power limits. The companies are pursuing both memory designs and storage products for robots and autonomous vehicles. The source provides no timeline, investment size or mass-production schedule; this development is an ongoing/planned R&D effort with no confirmed implementation or shipment status stated.
memory architecture for humanoid robotsmemory designsstorage productsMicron, Samsung Electronics and 3 totalDigiTimes Asia