The source does not state a specific date. According to the source, expanding investment in AI data centers is putting pressure on memory supply and demand across the automotive industry. As semiconductor companies prioritize high-bandwidth memory (HBM) and server products, automotive memory faces rising prices and tighter supplies. Against this backdrop, automakers' direct procurement, long-term partnerships, and in-house chip design are becoming increasingly strategic. No specific price change magnitude or figures are given in the source.
According to ZDNet Korea, reported on October 26, Samsung Electronics and SK Hynix are targeting the second quarter of 2027 to begin volume shipments of eight-layer HBM4 memory to Nvidia, as the AI chipmaker reassesses its memory strategy for next-generation Rubin Ultra accelerators. This is a plan/target and actual shipments have not yet occurred.
8-layer HBM4 memorySamsung Electronics, SK Hynix and 3 totalDigiTimes AsiaCapacity Change
China's semiconductor and electronics supply chains are reporting a wave of price increases: Goke Microelectronics has raised quotes for hybrid-packaged memory products, while Hygon is considering higher CPU and deep computing unit (DCU) prices. According to the source, the moves reflect rising costs for raw materials, components, and upstream supplies; however, the source states that whether they can help China escape deflationary pressure remains uncertain. Note: Goke's quote increase is an observed action, whereas Hygon's price increase is only under consideration and not confirmed as implemented.
hybrid-packaged memory productsCPUdeep computing unit (DCU)Goke Microelectronics, HygonDigiTimes AsiaPrice Movement
The source reports that the rapid expansion of AI data centers is driving demand beyond GPUs, memory chips, and advanced packaging. As power consumption in GPU clusters rises, data centers need not only more chips but also more efficient power delivery systems. Power plants and electrical grids outside data centers are also under pressure to close supply gaps, which could potentially tighten power semiconductor supplies and spread shortages to other applications. The source does not name specific manufacturers, part numbers, quantities, or dates, and describes the shortage only as a potential risk rather than a confirmed shortage.
This weekly roundup covers supply-chain shifts and rising demand across foldable smartphones, memory, energy storage, robotics, and AI infrastructure. Apple lifted its iPhone Duo shipment target after strong preorders, while the title also cites display issues; the source does not state the specific causal link between the display issues and the target revision. Memory makers faced conflicting forecasts over Chinese capacity and sustained AI demand. Taiwan advanced industrial microgrids and saw its first semiconductor strike, and Texas Instruments reported tightening analog supply. Chinese energy storage suppliers reportedly retreated from the US amid reciprocal technology and ownership restrictions. This is a roundup item with no specific numerical or price figures provided.
iPhone Duomemoryanalog chipsApple, Texas Instruments and 4 totalDigiTimes Asia
Related manufacturers
Apple, Texas Instruments, memory makers, Chinese energy storage suppliers
Anthropic filed a preliminary IPO registration statement with the US Securities and Exchange Commission, in which it describes how much of its capacity depends on a small group of chip and memory suppliers, most of them in East Asia. The filing puts TSMC, HBM and direct leasing at the center of its AI compute risk disclosure. This is a risk statement in a preliminary registration document; it does not report any capacity change, halt or price movement.
Cadence Design Systems used its third-quarter earnings call to argue that demand for chip design tools is no longer tied only to the AI hardware buildout, pointing to analog and memory chipmakers, system companies, and new entrants such as space and finance firms designing their own silicon. On the October 26 call, analysts pressed two questions that will shape the coming year: how much growth comes from agentic AI rather than hardware, and whether Cadence can match the long-term targets rival Synopsys set a month earlier.
Spanish semiconductor metrology equipment maker Wooptix plans to supply its Phemet wafer metrology system to a South Korean semiconductor manufacturer; the customer's identity was not disclosed. Marco Franchi, technical marketing manager at Wooptix, said the company will begin deploying equipment at customer sites next year to validate its suitability for their processes, with the goal of entering mass-production lines within two to three years. Samsung Ventures led an investment in the company last year. Phemet is an automated metrology system that measures the shape of 300-millimeter wafers, including bow and warpage; it captures an image of an entire wafer in less than one second and offers subnanometer height measurement resolution. The system illuminates the wafer with LEDs and calculates its surface profile from phase differences in reflected light, using technology Wooptix calls Wavefront Phase Imaging (WFPI). The company unveiled Phemet in November 2025 and installed its first system at French semiconductor research institute CEA-Leti in May. Wooptix plans to secure logic semiconductor customers in Korea before expanding into memory, because wafer alignment and shape control have become more challenging with gate-all-around (GAA) transistors and backside power delivery network (BSPDN) processes; it subsequently plans to expand into advanced packaging applications including hybrid bonding and is considering miniaturizing the equipment for die-to-wafer (D2W) and die-to-die (D2D) processes. Founded in 2016, Wooptix raised more than 10 million euros in a Series C funding round in February 2025, jointly led by Samsung Ventures and the Spanish Society for Technological Transformation (SETT), with participation from existing investors including Intel Capital and Tokyo Electron (TEL) Venture Capital. Wooptix is headquartered in Tenerife, Spain, where it also operates manufacturing facilities, and maintains offices in Madrid and Grenoble, France; about 60% to 70% of its approximately 80 employees work in R&D, and the company plans to expand its workforce to around 100 by the end of this year or early next year.
wafer metrology equipment300-millimeter wafersWooptix, Samsung Ventures and 8 totalThe Elec
Related manufacturers
Wooptix, Samsung Ventures, Samsung Electronics, SK hynix, CEA-Leti, Intel Capital, Tokyo Electron (TEL) Venture Capital, SETT
Apple’s first foldable smartphone, the iPhone Duo, is reportedly facing quality concerns over display damage near the hinge. According to MacRumors on October 26, Apple acknowledged an issue affecting the inner displays of a small number of iPhone Duo units, but did not disclose the cause of the cracking or whether a fix is planned; affected customers have been able to obtain in-store replacements, though limited inventory has left some waiting. According to ZDNet (citing MacRumors), persistent hinge problems during development prompted supplier changes: U.S.-based Amphenol was initially the primary hinge supplier with Taiwan’s Shin Zu Shing as secondary; Shin Zu Shing took over after Amphenol’s production yields fell well below expectations, but reportedly also struggled, having to select units meeting Apple’s quality standards as “golden samples,” and these difficulties delayed iPhone Duo production. Reuters adds that iFixit, via a 3D hinge simulation based on teardown footage, patents, and CT scans, suggested a possible cause: a central support bar may fail to retract properly during folding, placing pressure on the inner display. According to NewsPim, Apple has reportedly asked Foxconn and component suppliers to raise the iPhone Duo shipment target for the next 12 months by 44%, from 9.7 million to 14 million units; industry sources suggest the increase reflects stronger-than-expected initial demand plus additional component stockpiling for potential assembly defects, and Foxconn’s final assembly yield was reportedly around 60% in September, with hinge-related defects potentially further increasing demand for replacement OLED panels. TrendForce notes early screen-failure reports could undermine consumer confidence, with the long-term impact largely depending on how widespread the issue is and how quickly Apple identifies the root cause and repairs or replaces affected units. Separately, per ZDNet, another potential supply constraint is T-glass, a high-end fiberglass yarn used in copper-clad laminates (CCLs) for PCBs, where Japan’s Nittobo holds a near-monopoly and is prioritizing shipments for AI chips made by companies such as NVIDIA, potentially adding pressure to Apple’s supply chain.
hingeinner OLED displayT-glassApple, Amphenol and 6 totalTrendForce
Related manufacturers
Apple, Amphenol, Shin Zu Shing, Foxconn, Nittobo, NVIDIA
According to ZDNet, Samsung and SK hynix are preparing to ship 8-Hi HBM4 for Rubin Ultra in 2Q27, departing from the original 12-Hi HBM4E plan; 8-Hi HBM4 was initially absent from NVIDIA's plans, but talks gained traction in 3Q26. The source cites thermal challenges and lower yields in 12-Hi stacks, potentially easing supply constraints. Although both Samsung and SK hynix have completed NVIDIA's qualification for 12-Hi HBM4, their 8-Hi products require separate certification; a source said NVIDIA is expected to deploy both 8-Hi HBM4 and 8-Hi HBM4E in Rubin Ultra-based NVL rack-scale systems depending on rack configuration. TrendForce says 8-Hi configurations use fewer DRAM dies, lowering cost per stack and GPU bill of materials, and given tight HBM supply, 8-Hi setups are expected to be a priority for evaluation by many GPU and ASIC vendors in 2027; ZDNet reports 12-Hi HBM4 remains mainstream in 2026, with 8-Hi adoption expected to rise sharply from mid-2027. Economy Tribune, citing Daishin Securities, suggests Anthropic's in-house AI chip could also feature 8-Hi HBM4, raising the prospect of Samsung supplying both foundry services and memory. Separately, per Wccftech, NVIDIA trimmed Vera Rubin's HBM4 bandwidth specifications: an archived September 1 version listed the Vera Rubin NVL72 system with 20.7 TB of HBM4 capacity and 1,580 TB/s bandwidth, the Vera Rubin Superchip at 576 GB and 44 TB/s, and each Rubin GPU at 288 GB and 22 TB/s; NVIDIA has since lowered per-GPU HBM4 bandwidth to 19.2 TB/s and NVLink 6 throughput from the originally advertised 3.6 TB/s to 3 TB/s, cuts of roughly 13% and 17% respectively, and up to 26% for HGX Rubin NVL8 systems, with changes dating back to September. IT Home notes NVIDIA revised the Vera CPU memory specification from a fixed 1.5 TB of LPDDR5X per chip to 'up to 1.5 TB', and that lowering bandwidth requirements could allow more HBM4 products to qualify for Rubin GPUs, potentially boosting overall production output.
HBM4HBM4ELPDDR5XNVIDIA, Samsung and 4 totalTrendForceCapacity Change
Intel is actively planning the "Raptor Lake Next" chips as an update to its Socket LGA-1700 desktop processors. These chips are essential for PC buyers who are limited to the decade-old DDR4 memory standard due to the high prices of DDR5 memory, especially since the current Core Ultra "Arrow Lake" processors do not support DDR4. Two "Raptor Lake Next" chips have appeared in shipping manifests, which usually indicate that the CPUs are being shipped as samples to customers or as part of a production run returning to Intel, suggesting a nearby launch. Four SKUs have been identified, labeled 99DLMV, 99DLMT, 99DLMW, and 99DLMX, but details exist on only two models: the 99DLMV is a 16-core design with 8 P-Cores and 8 E-Cores, a clock speed of 3.5 GHz, 30 MB of CPU cache, and a TDP of up to 125 W; the 99DLMT is a 20-core SKU with 8 P-Cores and 12 E-Cores, running at 2.1 GHz, with a CPU cache capacity of 33 MB, and a TDP of 65 W. These leaked models align with previous rumors, such as the one suggesting that Intel plans to replace the Core i5-14600K with a new "Raptor Lake Next" chip featuring 8 P-Cores and 8 E-Cores, so the 99DLMV SKU might be the one previously speculated about.
Since the launch of TSMC's N5 5 nm process in 2020, the size of the SRAM 6T bitcell has remained around 0.021 µm², with logic transistor density increasing but memory not seeing similar advancements. With the A14 node, the 6T SRAM bitcell is expected to shrink significantly to 0.017 µm², a 19% reduction, with production set for 2028. TSMC is currently conducting pilot production to assess the viability of the node, enabling customers to evaluate how their designs will perform in TSMC's production environment; the progress of A14 production is reported as promising, with timelines advancing due to early successes. If pilot production continues smoothly without major yield or production issues, risk production is set to commence in 2027, followed by high-volume manufacturing in 2028; if no significant challenges arise next year, TSMC may even accelerate the production schedule by a few months.
Reported on 2026-10-27: two developments highlight growing momentum in Micro LED optical interconnect. U.S. smart glasses and optical waveguide developer Vuzix unveiled its Vuzix Causeway optical interconnect evaluation platform, based on its proprietary diffractive waveguide technology, at the 2026 OCP Global Summit (held October 12–15, 2026 in San Jose, California), targeting AI data center, semiconductor, and photonics applications; the current evaluation platform supports 19,200 parallel optical paths over an optical path length of approximately 30mm, and once light sources, detectors, and system integration are completed, the technology is expected to support aggregate bandwidth in the multi-terabit range (expected, not yet achieved), with a waveguide architecture compatible with Micro LED and VCSEL light sources; Vuzix is making evaluation units available to qualified industry partners and shipped its first Causeway waveguide bridge samples to selected customers in August. On the funding side: on October 14, Beijing-based Xinghuo Chenguang Technology announced completion of its first funding round, led by Sequoia China with San'an Optoelectronics participating as a follow-on investor and Yunxiu Capital as exclusive financial advisor for subsequent funding rounds; the amount raised was not disclosed. Xinghuo Chenguang develops Micro LED-based optical interconnect chips, targeting high-speed, low-power data exchange between chips and between computing and memory in AI and high-performance computing systems. On technology progress: on September 28, Xinghuo Chenguang, Yuanxu Optoelectronics, and Tsinghua University announced a milestone in Micro LED optical interconnect chip R&D joint testing by Tsinghua University and Xinghuo Chenguang showed a Micro LED chip sample achieved a -3 dB bandwidth of 3.5 GHz at a current density of 500 A/cm², demonstrating high-speed response at the 3 GHz level. In the next phase the three parties will focus on device consistency, array integration, and packaging interconnects, and conduct link-level testing to validate communication performance.
Micro LED optical interconnect chipoptical interconnect evaluation platformdiffractive waveguideVuzix, San'an Optoelectronics and 6 totalTrendForcePartnership/M&A
DapuStor has put together a 5-page explainer document showing how tiering evicted KV cache contents to NVMe SSDs can solve the recomputation delay problem. The document says offloading large KV Cache datasets to a more cost-effective external storage tier is emerging as a practical approach for scaling inference clusters, and explains how KV Cache works in LLM inference and how NVMe SSDs can help build a cost-efficient storage layer for AI infrastructure. It discusses the mechanisms used by vLLM and LMCache, explained with text, diagrams and Python code examples, noting both support packing KV Cache data from multiple tokens for transfer to improve memory and I/O efficiency, and that external storage systems can use these larger chunks to generate flash-friendly, sequential large-block I/O patterns, improving bandwidth utilization on NVMe SSDs. It notes PCIe gen5 NVMe SSDs have capacities rising to 245 TB, hopefully beyond that next year, offering scope for building petabyte-level external storage KV caches with good bandwidth and high capacity.
Nvidia has effectively sent JEDEC back to the drawing board with its HBM standard: Nvidia revolted against HBM memory controller functionality being in its GPU chip and, in its NVHBM custom HBM standard, moved it to the HBM base die unit, freeing up space for more GPU cores; the change is part of its August NVLInk Fusion announcement. Nvidia claims (a vendor claim, not a verified achieved result) that, compared with standard HBM4E, NVHBM delivers up to 30 percent greater memory bandwidth, 15 percent lower HBM power consumption, and frees up to 25 percent more area on its GPU compute die; this is specific to Nvidia and is not an industry standard. According to reported Morgan Stanley data, Nvidia will be responsible for purchasing 37 percent of the global HBM supply in 2027, so the three HBM suppliers — Samsung, SK Hynix and Micron — are supporting NVHBM and even let Nvidia dictate that they must use TSMC's 3nm foundry process; Reuters reported Samsung will accede to this request, but per Seoul Economic Daily, Samsung would still build JEDEC standard HBM in-house for other customers. Amazon's Annapurna Labs is also supporting NVHBM as an Nvidia NVlink partner. JEDEC has not issued any public comment about NVHBM; when JEDEC announced the HBM4 standard in April last year, the HBM subcommittee chair was Barry Wagner, Director of Technical Marketing at Nvidia. Beyond the stated reason of freeing GPU-core space and moving the memory controller, the source does not state another cause.
HBMHBM4EHBM4Nvidia, Samsung and 5 totalBlocks & Files
This is a background technical explainer about TSMC's CoWoS-S (Chip-on-Wafer-on-Substrate with a silicon interposer) 2.5D integration platform, which places large logic dies or chiplets beside multiple high-bandwidth-memory stacks and connects them through dense wiring in a silicon interposer, producing multi-terabyte-per-second memory interfaces. TSMC reports the platform has been in production since 2012 and supports silicon interposers reaching approximately 3.3 times reticle size; its fifth-generation implementation demonstrated an interposer of about 2,500 square millimeters capable of accommodating multiple logic chips and eight HBM stacks. The article also describes power-integrity features (embedded deep-trench capacitors), thermal and mechanical engineering challenges, and notes that packaging capacity determines how quickly cloud providers can deploy new computing clusters. The source does not state the cause of any event, as this is background technology analysis with no price movement, capacity change, or policy event reported.
TSMC CoWoS-S (Chip-on-Wafer-on-Substrate with silicon interposer)2.5D integration platformsilicon interposerTSMCSemiWiki
Flex has completed its acquisition of EPC Power, a provider of intelligent power conversion solutions for data centers and electrical grid applications. The acquisition expands Flex's Cloud and Power Infrastructure portfolio and strengthens its power conversion, grid stabilization, and next-generation AI infrastructure support capabilities. EPC Power develops power conversion systems combining proprietary hardware, software, and control technologies, supported by US-based engineering and manufacturing operations, and has more than 15 GW of deployed capacity. The source states that AI data centers are increasing rack power density and placing greater demands on electrical distribution and conversion infrastructure, and Flex is expanding its portfolio, including the transition toward 800V power architectures for next-generation data centers; EPC Power's power conversion platform is engineered to support these emerging architectures. Flex also announced plans to spin off its Cloud and Power Infrastructure segment into an independent, publicly traded company, Axiom Solutions International, Inc., with plans to complete the separation in the first calendar quarter of 2027; this spin-off is a proposed transaction and not yet completed. The source does not state the transaction value of the acquisition.
power conversionFlex, EPC PowerPower Electronics NewsPartnership/M&A
Per Tom's Hardware on 26 October 2026, Micron outlined its next-generation DRAM technology plans: the company intends to introduce wafer bonding with its upcoming 1ε DRAM process technology and adopt High-NA EUV lithography (together with new materials) for the subsequent ζÅ (1st generation sub-10nm-class DRAM node) and ηÅ (2nd generation sub-10nm-class DRAM node) generations; it has not disclosed how it will implement wafer bonding or what improvements it expects. Micron's current 1γ DRAM process is already in high-volume manufacturing, while its successor 1δ is scheduled to enter volume production in the second half of 2027, promising a mid-20% increase in bit density and optimized for future AI memory products including HBM5, vHBM, and vEIM. Micron is also developing 3D DRAM (generations 3D1 and 3D2 on its roadmap, with architectures and launch schedules undisclosed) as well as vertical high-bandwidth memory (vHBM), vertical edge inference memory (vEIM), and various custom HBM (cHBM) implementations; the 1st generation vEIM targets 2 TB/s bandwidth at <1pJ/bit energy, in line with what HBM4 currently offers (at 8 GT/s over a 2,048-bit interface). The company has not disclosed when vHBM, vEIM, or cHBM will enter commercial production. Micron president and chief technology and products officer Scott DeBoer said 'DRAM is nearing atomic limits at this point,' adding that the company has confidence in several more planar nodes and will introduce 3D DRAM only at the optimal time from a cost and performance point of view. All items are plans/under development, not achieved results.
Power Electronics News published a roundup of this week's articles covering practical EMI guidance for power converters, FinFET-based power devices, and simulation-driven thermal modeling for SiC and GaN converters. The roundup also lists news items: Navitas launched a 2300-V SiC power module for grid infrastructure, with the 2300 V SiC technology targeting higher efficiency and power density in AI data centers, energy storage, and grid applications; Allegro introduced 48V power management and precision position sensors for robotics, helping humanoid robots with integration, motion control, and functional safety; EPC GaN FETs enable a 4 kW high-efficiency converter, where the dual-phase EVAL-LT7930-AZ combines ADI's LT7930 controller with EPC2361 transistors for high-current power conversion; STMicroelectronics launched a QML-V qualified LVDS receiver, the RHFLVDS42, supporting data rates up to 600Mbps, 300krad(Si) radiation resistance, and 8kV ESD immunity for aerospace systems; onsemi and Sungrow target 99.3% efficiency in utility-scale BESS, where the PowerTitan 3.0 platform supports conversion units up to 450 kW and could save over 475 MWh annually in a 100 MW installation. The articles section also covers a GaN-based dual-side cooled package for 650-V GaN in 800-V AI data centers. This item is an informational roundup with no price or supply-demand data.
SiCGaNFinFETNavitas, Allegro and 9 totalPower Electronics News
Toshiba Electronics Europe GmbH has introduced the TCKE5 Series of electronic fuse ICs (eFuses), designed to protect low-voltage power lines in space-constrained electronic equipment. The series includes four models (TCKE501UA, TCKE501UL, TCKE502UA, TCKE502UL), operates from 1.7V to 5.5V, and supports 1.8V, 3.3V, and 5V supply rails in applications such as SD memory cards, USB and HDMI devices, laptop PCs, and gaming consoles. The devices combine overcurrent detection and short-circuit protection in a compact SOT-353F (UFV) package; an external resistor sets the overcurrent detection threshold, and the typical overcurrent mask time is 2.4ms. The UA variants automatically retry operation after a fault, while the UL variants latch off and require an external signal to restart. All four devices support a maximum DC output current of 1.0A, and each IC measures 2.0mm × 2.1mm × 0.7mm (typ.). For input voltages from 5V to 5.5V, Toshiba advises following the datasheet recommendations for output capacitance or using an external Schottky barrier diode to manage voltage transients during short-circuit protection. Shipments of the TCKE5 Series have started.
eFuse ICs (electronic fuse ICs)Toshiba Electronics Europe GmbHPower Electronics News