Samsung Foundry may be on the verge of securing a deal to manufacture Anthropic's AI ASIC on its SF2 2 nm node, with an initial volume of around 200,000 chips, designed by Broadcom targeting approximately 4,000 TOPS of INT8 compute and a TDP of 1,300 W per chip, supported by either 192 GB or 288 GB of HBM3E, using I-Cube 2.5D packaging; the chips are currently produced in South Korea and a new facility is planned in Taylor, Texas.
Anthropic AI ASIC on 2 nm nodeSamsung Foundry, BroadcomTechPowerUpPartnership/M&A
On October 7, Boss Semiconductor said it will work with Japan's Mirise Technologies to develop chiplet interconnect technology for automotive applications. Boss Semiconductor will support Mirise Technologies' automotive research and development (R&D) project, providing expertise in automotive system-on-chip (SoC) and chiplet design. The companies did not disclose the duration or scale of the collaboration. Mirise Technologies is researching chiplet interconnect technology for automotive applications; chiplets divide functions traditionally integrated into a single semiconductor among multiple smaller chips connected into one system, an approach that can improve yield and cost efficiency while expanding performance and functionality. As background, chiplets have traditionally been used mainly in large, high-performance server chips such as GPUs, and more recently the technology has been adopted in automotive applications as vehicles incorporate functions requiring high-performance computing, including autonomous driving and advanced driver assistance systems (ADAS).
This is a technology overview article on engineered (synthetic) diamond for data center power electronics. The AFCOM State of the Data Center report indicates average rack density has reached 27 kW per rack, making thermal bottlenecks the main limiting factor, while operators migrate to 800 V DC bus architectures. Diamond's thermal conductivity is ~2,200-2,400 W/m·K (up to 3,300 W/m·K for isotopically enriched samples), with a 5.5 eV bandgap and theoretical breakdown field of about 5–10 MV/cm; laboratory Schottky diodes have reached close to 8 MV/cm. Coherent Corp. introduced next-generation bondable diamond thermal management solutions, allowing direct fusion, hybrid, or metallic bonding to silicon, silicon carbide, and gallium nitride, reducing interface thermal resistance by as much as 99 percent for die sizes up to 100 mm². In June 2026, Element Six (part of the De Beers Group) and Tokyo-based precision components maker Orbray announced a reproducible process for 3-inch wafer-scale single-crystal diamond, with 4-inch substrates in development; Element Six is also preparing 2-inch wafers for thermal-bonding volume production at its CVD facility in Gresham, Oregon. Diamond Foundry opened a commercial production facility in Trujillo, Spain, in 2025 and is slowly ramping up production. Japan's Ookuma Diamond Device has built what it calls the world's first diamond semiconductor factory in Ōkuma, Fukushima, and is planning to mass-produce diamond-based semiconductor and power devices for nuclear decommissioning. Power Diamond Systems gave the first public verification of packaged diamond semiconductor performance at SEMICON Japan 2025, showing diamond-based power MOSFETs, and hopes to bring the technology to market in the 2030s. Diamond Quanta reported electron mobility greater than 555 cm²/V·s in polycrystalline diamond. The article states that diamond's function today is best viewed as a thermal enabler placed over proven GaN and SiC switches, not a drop-in replacement device.
engineered (synthetic) diamondGaN-on-diamonddiamond-bonded SiCCoherent Corp., Element Six and 7 totalPower Electronics News
Related manufacturers
Coherent Corp., Element Six, Orbray, Diamond Foundry, Ookuma Diamond Device, Power Diamond Systems, Diamond Quanta
Micron has locked in most of its 2027 HBM supply at higher prices, signaling a strong demand outlook. Korean suppliers like Hanmi Semiconductor are poised to benefit from this expansion. Bullish for HBM supply chain.
HBMMicron Technology, Hanmi SemiconductorTrendForce Official (Market Data)Shortage Alert
AMD CEO Lisa Su announced plans to substantially increase chip supply in 2027, acknowledging current demand exceeds supply. She emphasized the need for more advanced wafer capacity to meet future needs. Bearish sentiment driven by future supply expansion plans.
Advanced Wafer CapacitySemiconductor ChipsAMD, TSMC and 4 totalTechPowerUpCapacity Change
Marvell and Siemens EDA presented a new verification methodology for 3D IC CoWoS systems at the TSMC OIP Forum, addressing reliability and ESD challenges in complex assemblies.
Inference now accounts for the majority of data-center AI workloads, but unlike training, it requires low latency and predictability. Existing training chips focused on peak FLOPS may not meet the strict limits of inference workloads. Watch: This shift highlights the demand for chips specifically designed for inference.
AI ProcessorsInference ChipsAI Chip MakersSemiWikiMarket Analysis
A consortium led by Aerix launched the MOSAIC-5G project to integrate UK 5G components, securing £3.1 million in Innovate UK funding. The initiative aims to simplify the deployment of standalone private networks using AI and advanced signal processing. Neutral: This R&D milestone focuses on technical integration and efficiency gains rather than immediate supply chain disruptions.
5G CoreRANSignal ProcessingAerix, Antevia Networks and 11 totalElectronics WeeklyTechnical
Related manufacturers
Aerix, Antevia Networks, AttoCore, Noema Signal Labs, Spry Fox Networks, RANsemi, Liverpool 5G, Bath & North East Somerset Council, Extend Robotics, Digital Catapult, Innovate UK
Researchers have dissected Huawei's Kirin 9050 Pro, revealing a 'LogicFolding' design using two vertically stacked dies instead of a traditional single-plane chip. This analysis highlights a new packaging approach for the Mate 90 Pro Max flagship SoC.
关注
(Technical trend, no immediate supply impact).
Kirin 9050 ProSoCHuawei, HiSiliconDigiTimes AsiaTechnical
WG Tech has initiated the second phase of investment for its TGV glass substrate production line, targeting an annual capacity of 1 million square meters. Analysts note that Chinese manufacturers are gaining an early lead in commercialization by prioritizing capacity construction before accelerating output and customer validation. Bearish: Significant capacity expansion increases supply pressure and risks oversupply.
JEDEC released JESD264, the first industry-wide reliability standard for silicon photonics, covering modulators and waveguides. This addresses the lack of optical-specific testing protocols compared to CMOS. TSMC is also advancing mass production of 200Gbps modulators, signaling industry progress.
Silicon PhotonicsModulatorsPhotodiodesJEDEC, TSMC and 4 totalTrendForceTechnical
Altman-backed Volantis plans to use photonic interposers to boost AI accelerator memory bandwidth to 240 TB/s and capacity to 10 TB, overcoming current electrical interconnect limitations.
AI AcceleratorPhotonic InterposerHBMVolantis, AMD and 3 totalThe RegisterTechnical
IBM's gen 5 FlashCore Modules (FCM5, IBM's proprietary SSDs featuring hardware compression, deduplication, die striping and cyber-attack detection, using QLC NAND with an SLC incoming write zone, with raw capacity points of 6.6, 12.2, 26.4, 52.8 and 105.6 TB) use Everspin MRAM instead of capacitors to protect against data loss from power failures. Because MRAM is non-volatile, the drives do not need super-capacitors to write consistency data to NAND on power loss; the metadata is held in MRAM and persists through power loss, allowing IBM to reclaim SuperCap space and populate it with more NAND chips to increase capacity. The report cites a page-21 FCM5 board illustration in the Redbook 'IBM FlashCore Module (FCM) Product Guide' showing an Everspin chip. The article also recalls that in April 2024 Everspin announced IBM chose its PERSYST EMD4E001G 1 Gb STT-MRAM chip for FlashCore Module 4 drives, specifically for data protection on power loss; prior FCM3s used up to 128 MB of Toggle MRAM for that purpose; and IBM has used a few hundred megabytes of Everspin MRAM inside FCMs for several years as a small, non-volatile write cache and journal. Everspin says its MRAM products have more than 2,000 customers, 20 years in production and more than 200 million chips shipped.
AI development is shifting focus from chip specifications to system-level design and ecosystems. Chipmakers are prioritizing system integration to maintain competitiveness. This trend indicates a strategic pivot in the semiconductor industry.
China stockpiled 343 DUV systems (270 NXT:1980i) spending over $13B in 2024-25, supporting 7nm production despite export controls. This confirms strong demand for ASML equipment, with China accounting for 33-41% of its net sales.
DUV Lithography SystemsImmersion DUV SystemsASML, Huawei and 3 totalTrendForceCapacity Change
ChipAgents utilizes AI agents to shorten timing closure feedback loops, improving engineering efficiency without replacing core synthesis or STA tools.
Advantest and Teradyne dominate the global memory testing equipment market, but HBM4 orders and the rise of Chinese suppliers like TBSTest are reshaping the landscape. Chinese firms secured over 300 systems from TBSTest and are targeting 15% market share by 2026, challenging the 80% import dependency. The increasing complexity of HBM4 is driving demand, with Digital Frontier and UniTest receiving over 280 billion KRW in orders.
HBM4DRAMNAND FlashAdvantest, Teradyne and 8 totalTrendForceMarket Analysis
Related manufacturers
Advantest, Teradyne, Samsung Electronics, SK hynix, Micron, TBSTest, Digital Frontier, UniTest
TSMC is exploring a joint venture with Elon Musk's Terafab to establish advanced semiconductor manufacturing in the US, potentially focusing on secondary capabilities rather than the latest nodes. This collaboration aims to provide dual-source expertise for Intel's 14A node, though the specific technology transfer details remain uncertain.
Advanced NodesTSMC, Terafab and 3 totalTechPowerUpPartnership/M&A
An engineering sample of the unreleased Ryzen 9 5900X3D has surfaced with 128 MB of L3 cache, running at 4.7 GHz. This differs from the dual-stack 192 MB prototype shown previously and requires specific BIOS support. Neutral: No immediate impact on current market supply or pricing.
Nvidia is testing PTFE and HC resin formulations for the Rubin Ultra NVL576 Switch Tray, targeting mass production in H2 2027. This shift aims to replace glass-based substrates for next-gen AI servers. Bullish for PTFE and HC resin material suppliers.