According to eeNews Europe, three previously closed US nuclear power plants are being prepared for recommissioning, potentially restoring a combined 2.25 GW of generating capacity. The restarts involve Holtec International, Constellation Energy and NextEra Energy, with Microsoft and Google among the companies supporting the projects (the source text is truncated regarding the means of support). The stated reason is that electricity demand from artificial intelligence and data centres continues to increase. This is background information on data-centre power supply, not directly tied to semiconductor component procurement, and the restarts remain at the preparation/planning stage with no indication of completion.
nuclear generating capacityHoltec International, Constellation Energy and 3 totaleeNews Europe
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Holtec International, Constellation Energy, NextEra Energy
At an event this week, Micron announced that its next-generation 3D NAND (G11), which it plans to enter mass production in 2H 2027, is set to offer three significant advantages: doubling storage density (approximately twice the bit density of G9, with 3D TLC going from 21 Gb/mm² to 42 Gb/mm²), increasing I/O performance by up to 50% versus the company's current-generation NAND memory (interface speed from 3,600 MT/s to 5,400 MT/s), and reducing data transfer energy consumption per bit by more than 25%. G11 will adopt wafer-on-wafer bonding, manufacturing the NAND array on a new 3D NAND node and the peripheral circuits and I/O on a logic process before bonding them together, and will transition to more than 400 NAND layers; Micron has not disclosed the exact number of active wordline layers or memory decks. Micron executive Scott DeBoer described G11 as the world's most advanced NAND, ramping in the second half of next year. Micron also expects to disclose more G11 technical details in 2027 and, beyond G11, is developing high-mobility materials and denser cell architectures to continue XYZ scaling; specific architectural details, density targets, or production schedules for post-G11 generations have not been disclosed. These are the company's stated plans and expectations; mass production has not yet occurred.
3D NANDG11 3D NANDMicronTom's HardwareCapacity Change
In an early Friday announcement dated 23 October 2026, SK hynix said it had decided to abandon plans for a potential initial public offering (IPO) of Solidigm, its U.S.-based enterprise SSD subsidiary, citing unfavorable stock market conditions and semiconductor share price trends. At the same time, SK hynix confirmed it plans to build a new fab for Solidigm in the U.S. to address growing demand for enterprise SSDs. SK hynix stated that although an IPO could have helped finance a new fab in the U.S., its subsidiary's expansion remains a priority; the company has discontinued its review of both pre-IPO financing and an IPO and will continue to evaluate alternative funding mechanisms. The source states that the planned fab's capacity, investment requirements, and construction schedule have not yet been disclosed. Solidigm specializes in high-capacity data center SSDs based on floating gate 3D QLC NAND memory, and its existing manufacturing capacity is barely sufficient to address its projected needs.
enterprise SSD3D QLC NANDSolidigm, SK hynixTom's HardwareCapacity Change
This is a roundup of the site's most popular articles from the last week. No. 5: Google and Synaptics have introduced the xMCU – an MCU combining heterogeneous, AI-native compute and acceleration with integrated high-bandwidth custom DRAM scalable to hundreds of megabytes; the Astra SR200 Series targets AI wearables and battery-powered sensing devices, enabling larger AI models and richer multimodal workloads entirely on-device. No. 4: According to the Data Centers Processor Market Monitor, Q3 2026, agentic AI is reviving datacenter CPU demand, with CPU revenues up 35%, ahead of AI ASICs (+23%) and GPUs (+13%); GPU and AI ASIC designers are scaling back their roadmaps, sometimes drastically, in response to the sharp rise in DRAM prices. No. 3: London neocloud startup Nscale has had another setback to its IPO plans as Microsoft pulled out of a deal to be the anchor tenant on Nscale's Loughton, Essex, datacentre; neither party gave any reason for the pull-out, but UK Power Networks has told Nscale it cannot supply enough power for the site until the early to mid 2030s. No. 2: Per the Seoul Economic Daily, Nvidia has asked Samsung, Hynix and Micron to use base dies made on TSMC's 3nm node for its custom HBM called NVHBM; the base die contains the logic layer at the bottom of the HBM stack that handles the memory controller and interface, and the source's report of Nvidia's reason is truncated. No. 1: According to a memo from CEO Cristiano Amon to employees seen by Reuters, Qualcomm is to lay off staff worldwide, with notifications to start next month; the number involved is not known, the company had 52k employees in September 2025, and the memo describes the lay-offs as "a performance-focused reduction after annual reviews".
xMCUNVHBM base dieHBMGoogle, Synaptics and 10 totalElectronics Weekly
An analysis article published 23 October 2026 reports that export controls keep ASML's most advanced EUV lithography machines out of China, so the country's chip industry relies on DUV lithography with multiple patterning to make advanced chips, at the cost of bigger dies, more defects, lower yields, longer manufacturing times and higher bills. Chris Mack, co-founder and CTO of Fractilia, said industry conventional wisdom held that three exposures on a 193 immersion tool cost about the same as one exposure on an EUV tool, and that at four masks EUV became more cost-effective. Teardowns of Huawei's Mate 60 Pro in 2023 found its Kirin 9000S processor made by SMIC using a second-generation 7nm-class process without EUV; analysis of Huawei's Kirin 9030 found SMIC had pushed its DUV-based process closer to 5nm-class density, though it continued to lag TSMC and Samsung leading processes. A June Morgan Stanley report estimated Chinese DRAM maker CXMT was producing only around one-third as many bits per wafer as Western competitors, with the older process node accounting for only about a third of that shortfall, and said access to lithography is a 'hard ceiling' on Chinese memory development. Micron's 1-alpha generation was developed without EUV, showing how far DUV can be stretched; Micron's newer 1-gamma DRAM process uses EUV, which Micron said achieves more than 30% greater bit density per wafer than its preceding 1-beta generation. Morgan Stanley assumes CXMT remains stuck on its 1-alpha process without EUV, yet raises its share of global DRAM bit supply from 14% in 2026 to 16% in 2028 by building more greenfield capacity, and expects China's AI chip self-sufficiency to rise from 42% in 2025 to 70% by 2030. Mack said he would be hard pressed to believe a three-nanometer or two-nanometer node is economically viable without EUV.
DUV lithographyEUV lithographyDRAMASML, SMIC and 7 totalTom's Hardware
At Nvidia's GTC event in Berlin, CEO Jensen Huang dismissed predictions of human extinction from AI, defended AI's job prospects, and pitched a $4,000 computer as the family robot. He claimed the AI datacenter boom has already created a million jobs in the United States, saying 'AI makes jobs, and hopefully doesn't take jobs.' Asked about Barclays Bank's announcement that same morning that it is chopping 5,000 workers and relying more on AI, he argued that technological change has always displaced some jobs while creating others. As financial background, Nvidia reported $215.9 billion in revenue for fiscal 2026 and $120 billion in net profit; in the first half of its fiscal 2027, those net profits were already close to the prior year's. Huang also put the price of licensing Nvidia's software stack at about $2,000 per GPU annually. The DGX Spark system he demonstrated contains a chip called N1X with 128 gigabytes of memory and is priced at $4,000. The source does not state the cause (the report is commentary on statements, with no single event cause).
On 22 October 2026, Micron announced it will abandon future 4F² DRAM after roughly two decades of research. The company says the architecture offers no meaningful density advantages, increases manufacturing complexity and costs, and has fundamental scaling limitations; CTO Scott DeBoer said capacitor pitch, not nominal transistor area, determines DRAM bit density, and that 4F² has no sustainable scaling path beyond a certain point, with 3D DRAM ultimately coming in instead. Micron acknowledges 4F² is technically feasible and that it has manufactured experimental devices based on the architecture. A 4F² cell theoretically occupies about 33% less area than a 6F² cell and could theoretically increase memory cells per wafer by 50%, but Micron argues these theoretical advantages do not necessarily translate into higher density in practice. Micron plans to continue scaling conventional 6F² DRAM by reducing capacitor pitch and shrinking process nodes; its upcoming 1δ process technology is scheduled to enter volume production in the second half of 2027 with a mid-20% improvement in bit density compared with its predecessor, and Micron plans to adopt High-NA EUV lithography for future DRAM generations. The company is also developing multiple generations of 3D DRAM production nodes but has not disclosed when the new architecture will enter commercial production. According to TechInsights, both Samsung and SK hynix still have 4F² memory cells in their roadmaps.
According to industry sources (reportedly, unconfirmed), Google is reportedly sticking with Intel EMIB-T despite substrate yields of only 35%, as the HumuFish variation's schedule tightens. Industry sources point to the HumuFish variation as a key area of concern, with reported yield problems. Uncertainty is growing over potential delays to Google's TPU v9; the source does not state that any delay has occurred and gives no specific timeline, with the reported yield problems serving as the stated cause of concern.
TPU v9HumuFishEMIB-T substrateGoogle, IntelTrendForce Official (Market Data)
PCB makers are expanding sustainability efforts as artificial intelligence (AI) and high-performance computing (HPC) drive demand for higher-performance boards. The industry still faces obstacles in securing affordable renewable power, validating low-carbon materials, and measuring emissions across its supply chain. Industry output is expected to exceed NT$1.13 trillion (US$34.63 billion) in 2026, putting pressure on the industry to balance growth with its sustainability goals.
At PyTorch Conference 2026, held in San Jose, California, on Oct. 20 local time, Google and Amazon unveiled the open-source frameworks TorchTPU and TorchNeuron, respectively, designed to simplify migrating existing AI applications from Nvidia GPUs to their own chips and to challenge Nvidia's CUDA ecosystem dominance. PyTorch, developed in 2016 primarily by Meta's (formerly Facebook's) AI research lab FAIR and used by approximately 85% of AI application developers worldwide, was originally designed around Nvidia GPUs and the CUDA platform, making migration to other chips difficult. TorchTPU, developed by Google in collaboration with Meta, according to Google, allows more than 98% of existing PyTorch models to run on TPUs simply by changing the device string in the code to model.to("tpu"), with conversion taking from a few minutes to a few days, and Google said it enabled TPUs to operate as native devices on an equal footing with GPUs and CPUs at the core PyTorch level. AWS's TorchNeuron similarly allows PyTorch-based AI models to run directly on AWS's Trainium AI chips, requiring developers to change only a few lines of device settings, replacing Nvidia's cuda with AWS's neuron. Amazon has released TorchNeuron as a public beta through GitHub under the Apache 2.0 open-source license and is also contributing code directly to the main PyTorch open-source project. Previously, migrating AI applications optimized for Nvidia's ecosystem to Google's or Amazon's proprietary AI chips took at least several days and, in more complex cases, several months; the new tools effectively remove these time and cost barriers. As TorchNeuron, TorchTPU and similar tools gain adoption, dedicated AI chips are expected to compete primarily on underlying performance, power efficiency and pricing, though additional time will be needed to verify compatibility, performance and costs for individual models.
Nvidia CUDATorchTPUTorchNeuronGoogle, Amazon and 5 totalThe Elec
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Google, Amazon, Meta, Nvidia, Amazon Web Services (AWS)
On 21 October 2026 (Wednesday), Intel announced that it had started installing production tools at its Fab 62 in Arizona, with the fab on track for mass production by late 2028; however, the company has not disclosed when it intends to begin high-volume production, the planned wafer processing capacity, the capital expenditures required to complete the facility, and it has not officially assigned Intel 14A to Fab 62 (Fab 62 remains unassigned, while Fab 52 has been designated for Intel 18A). Per Intel's manufacturing roadmap disclosed earlier this year, Fab 62 will be able to make chips on 18A, 18A-P, and 14A nodes. Intel also confirmed that it has integrated High-NA EUV lithography into high-volume manufacturing (HVM), used to produce select tiles for Panther Lake CPUs at its D1X fab in Oregon; Intel has not explicitly confirmed whether High-NA EUV scanners are currently used to produce the same circuits as Low-NA EUV machines. In addition, construction workers recently installed the first major structural truss at the first fab of the Ohio One complex in New Albany, Ohio, but Intel did not provide an updated construction schedule, disclose when the first fab is expected to begin operations, or reveal which process technology it will use or its estimated capacity. The source does not state the cause (this is a capacity expansion progress update, not a price or disruption event).
Synaptics introduced the Astra SR200 series of xMCUs, which run multimodal AI workloads entirely on-device, combining heterogeneous, AI-native compute and acceleration with integrated high-bandwidth custom DRAM scalable to hundreds of Mbytes. The devices are powered by Synaptics' Torq AI engine with Google Research's transformer-capable Coral NPU and deliver up to 400 GOPS of AI inference. The series comprises three pin-compatible product lines: the SR210 reaches 200 GOPS for always-on voice and sensing; the SR230 adds vision, display, and optional audio at 300 GOPS; and the SR250 provides 400 GOPS with dual vision and display paths for demanding edge applications. The devices also feature Arm Cortex-M85 and Cortex-M52 cores, integrated vision and audio capabilities, and hardware-rooted security, with a tiered architecture pairing up to 8 Mbytes of SRAM with extensible, high-bandwidth custom DRAM that Synaptics says runs workloads at one-third the power of typical system DRAM.
Google reportedly remains committed to Intel's EMIB-T for HumuFish despite poor substrate yields. According to industry sources, EMIB-T substrate yields were around 35% in 3Q26, well short of the 50% target set for year-end; the reported causes are thermal expansion differences between ABF substrates and embedded silicon bridges that make precise alignment difficult during high-temperature processing, and NCF (Non-Conductive Film) applied beneath the bridges' TSVs trapping air bubbles during bonding, potentially weakening adhesion. Despite market rumors of a HumuFish delay and the possibility of a switch to TSMC's CoWoS-L, supply chain checks indicate HumuFish remains '100%' committed to EMIB-T. Intel has adjusted its substrate electroplating process, and suppliers including Ibiden, Unimicron, and Shinko continue working to improve yields. Google's TPU v9 lineup is confirmed to include three variants: Broadcom-designed WhaleFish (expected to adopt TSMC's CoWoS-L, with mass production slated for 2H27), MediaTek-designed HumuFish (set for 1H28 mass production, relying exclusively on Intel's EMIB-T), and TriggerFish (also planned to use EMIB-T, with production targeted for 2H28 or later). Per TechNews citing analyst Ming-Chi Kuo, TriggerFish is positioned as an upgraded TPU v9 with stronger inference capabilities and features three key upgrades over HumuFish: 2–3 times the SRAM capacity, an additional simulation die, and a shift to HBM4E from HumuFish's HBM4. On delays, the tape-out of Google-designed Compute Die A, built on TSMC's N2 process, has been pushed back to late October while other dies remain on schedule, and the delay is expected to push back trial production of the complete package; Commercial Times further notes the MediaTek-involved Google TPU v9 project (HumuFish) could see its tape-out pushed back to January 2027 due to design revisions, potentially delaying shipments until 1Q28. With HumuFish not slated for mass production until 1H28, the supply chain still has time to address EMIB-T's remaining issues, but a tape-out slip to January 2027 could compress that cushion.
Intel EMIB-T substratesABF substratesNCF (Non-Conductive Film)Google, Intel and 8 totalTrendForce
Elon Musk said on October 20, during a live broadcast of SpaceX's Q3 2026 earnings call on X, that ASML and other critical semiconductor equipment suppliers have expedited shipments to the Terafab semiconductor manufacturing facility, a joint megaproject between Tesla and SpaceX, to support his aggressive timeline. He said the company is targeting volume chip production at Terafab's primary facility in Gibbons Creek, Texas, by the third or fourth quarter of 2028, emphasizing that the timeline is highly aspirational and carries 'big error bars'; SpaceX plans to manufacture its first experimental test chip at its research fabrication facility in Austin, Texas, around Q2 2027. Terafab will use traditional extreme ultraviolet (EUV) lithography systems utilizing Intel's 14A manufacturing node; Intel officially joined the Terafab venture in April 2026 to co-develop and refactor silicon fabrication technology. According to unofficial sources, Terafab's first EUV tool was reportedly slated for delivery in mid-2027, and it remains unclear if this is the expedited timeline Musk referred to. Other major suppliers include Applied Materials, Lam Research, and KLA Corporation, as well as Japan's Tokyo Electron; Tesla and SpaceX are also in talks with about 10 South Korean equipment makers, including Hanmi Semiconductor (advanced packaging equipment) and HPSP (high-pressure hydrogen annealing equipment). Musk also outlined AI compute goals: 2.5 to 3 GW of computing capacity active by the end of 2026, a total of 13 GW by the end of 2027, and plans to bring a 440,000-GPU Nvidia 'Vera Rubin' training cluster online by the end of Q2 2027. The event remains a plan/target and volume production has not been achieved.
EUV lithography systemslogic chipsmemoryASML, Tesla and 11 totalTom's HardwareCapacity Change
At GTC Berlin (report published the week of 21 Oct 2026), Nvidia unveiled modular datacenter containers called DSX pods, as a plan: starting in 2027, Nvidia and its partners will offer Vera Rubin rack systems fully plumbed, wired, and ready for deployment in modular bit barns. Each DSX pod weighs 28 metric tons and contains seven Vera Rubin NVL72 racks packing 504 GPUs and 252 Vera CPUs, built by partners such as HPE, Dell, and Schneider Electric, with customization between vendors such as HPE versus Dell and Eaton versus Schneider. Nvidia says the pods will cut datacenter deployment times from six months to as little as two weeks because every fitting, cable, and component will be validated before leaving the factory — a vendor claim and a plan, not an achieved result. The first DSX pods powered by Vera Rubin rack systems are expected to roll off the production line early next year. Nvidia also laid out new DSX specs for waterless datacenters using closed-loop coolants and dry coolers rather than water-thirsty cooling towers. The source frames this as part of the company's ongoing effort to quash supply chain challenges before they start eating into revenues.
Synaptics Incorporated (Nasdaq: SYNA) introduced the Astra SR200 Series, launching the xMCU, a new class of microcontrollers that runs multimodal Edge AI. The xMCU combines heterogeneous, AI-native compute and acceleration with integrated high-bandwidth custom DRAM scalable to hundreds of megabytes, which the company says enables larger AI models and richer multimodal workloads to run entirely on-device. The SR200 Series is designed for the next generation of AI wearables, battery-powered sensing devices, connected cameras, streamers, and industrial vision and voice systems. It is powered by the Synaptics Torq AI engine, features the Coral NPU from Google Research, and includes the industry's first pairing of the Arm Cortex-M85 and Cortex-M52, together with integrated vision and audio capabilities and hardware-rooted security. This is a product announcement and does not involve price or supply-demand changes.
Astra SR200 Series multimodal Edge AI processors (xMCU)SynapticsTechPowerUp
The US imposed sanctions on five Chinese entities tied to ex-Google engineer Linwei Ding over theft of trade secrets. The action follows his conviction for stealing confidential AI technology from Google, apparently to benefit Chinese firms. The sanctions have been imposed (effective); the source does not name the five Chinese entities.
Meta revealed this week that more than 11 percent of the GPUs at its Prometheus supercluster in New Albany, Ohio, are either dead or sitting idle, waiting to step in when a GPU fails. Prometheus is among Meta's largest compute deployments to date, powered by Nvidia's Grace Blackwell and (soon) Vera Rubin rack systems, and Meta says the supercluster will eventually scale to a gigawatt of capacity spanning about a million accelerators. The cluster is currently powered by a combination of GB200 and GB300 systems, each with 72 GPUs per NVLink domain, but only 64 are ever in use at any given moment, with the other eight essentially hot spares; Meta did this because a single failed GPU would take out an entire rack and interrupt the training run. Meta says that when it began the first phase of the Prometheus deployment it was experiencing roughly 1,000 interruptions per day for every 8,000 GPUs, and in the year since it has cut interruptions by 99 percent, to about 11 per day per 8,000 GPUs. Meta also says it achieved more than 85 percent goodput for pretraining and more than 90 percent for reinforcement learning on its latest model Muse Wonder, and as it works toward a million GPUs it hopes to reduce the interruption rate to just two per day for every 8,000 GPUs, or about 100,000 GPU-hours mean time between interrupts. The source does not state any implication for GPU market supply or demand.
At Synaptics Tech Day 2026 on October 20, 2026, Synaptics introduced what it calls a new class of microcontroller (xMCU), the Astra SR200 series, positioned between traditional MCUs and application processors. The family includes three pin-compatible members: the SR210 (200 GOPS, for voice and sensing), the SR230 (300 GOPS, for vision and display systems), and the SR250 (400 GOPS, for multimodal applications). The SR200 is built around an Arm Cortex-M85 processor running at up to 800MHz plus a lower-power Cortex-M52, with up to 8MB of SRAM and up to 256MB of high-bandwidth custom DRAM. Its Torq NPU subsystem combines Synaptics' own Torq T2 with Google Research's Coral NPU; the Coral NPU is based on the open RISC-V architecture, and Google Research is making the architecture available as open-source IP. Synaptics was the first commercial adopter and integrator of Google's Coral NPU IP, incorporating the first-generation architecture into its Astra SL family in 2025; the SR200 series incorporates the second-generation Coral NPU, which adds SIMD vector processing to improve performance and energy efficiency. Within the joint Coralboard development platform family, the Coralboard SL, based on the Astra SL2619 processor (dual Arm Cortex-A55 cores and a 1 TOPS NPU subsystem combining Torq T1 with first-generation Coral NPU), is now generally available through DigiKey following an initial limited release; the Coralboard SR, based on the new SR250, is being demonstrated in samples at Tech Day 2026, with broader availability anticipated in the first half of 2027. The Coralboard design incorporates a production-grade system-on-module (SoM) from Poland-based embedded hardware specialist GRINN. Google Research has further enhancements to the Coral NPU architecture in the pipeline, and Synaptics plans to continue introducing new processors and development boards as the technology evolves.
edge AI microcontroller (xMCU)neural processing unit (NPU) subsystemdevelopment boardSynaptics, Google Research and 3 totalEE Journal
According to Tom's Hardware on 20 October 2026, electronics hobbyist Blighted Agent converted a SK hynix 2x 16GB DDR5-5600 SODIMM (laptop memory) kit bought on Facebook Marketplace for $120 into a 2x 16GB DDR5-7800 desktop kit, claimed to be worth around $1,000, by removing the memory ICs with a hot air station, adding 0.45mm leaded solder balls, mounting them on blank DDR5 desktop PCBs bought from AliExpress for around $16 each, and adding heatsinks for around $18; the total bill of materials came to $175. The modules used what he believed to be SK hynix A-die ICs. The finished DIMMs were recognized in an Asus ROG Maximus Z790 Apex Encore motherboard as two 'SK hynix 16,384MB 5600MHz' modules, and after tuning ran rock-steady at DDR5-7800 CL38 and 1.40V, verified by 90 minutes of stress testing; the hobbyist notes the rework carries many risks and he lacks testing equipment to locate a faulty individual IC. On prices, he checked eBay U.S. where the best deal for a used 32GB kit was $320, while the best price for a new 32GB DDR5-6000 kit seemed to be $449 at the time of writing. The article also notes Russian enthusiast VIK-on completed a similar project earlier this year, flashing custom firmware for auto-detected 6400 MT/s XMP support. The article states that in late 2026 DDR5 RAM continues to be too expensive; the source does not state the cause.