Nvidia is expanding its chip business beyond technology giants into emerging AI markets such as new cloud providers, and has become a "central bank" helping these companies expand by backing customers and demand. As Nvidia-backed AI cloud companies come under pressure, concerns are growing over how long Nvidia can sustain this role. The source states no figures, dates, or cause.
Samsung Electronics has disclosed a patent application targeting GPU memory shortages when multiple users simultaneously submit requests to AI servers. By calculating data-transfer costs between GPUs and CPUs and minimizing unnecessary transfers, the technology is designed to enable AI servers to process more user requests quickly within limited memory capacity, without adding GPUs. This is the disclosure of a patent application, i.e., a proposed technical solution, not an implemented product or capacity change.
Taiwan pump maker Walrus Pump indicates that liquid cooling is becoming mainstream in AI servers, and as chip heat rises, data-center customers are assessing pumps that can move 100 metric tons of water per hour. The company expects slower ordering momentum to limit its technology-pump revenue growth, while broader adoption could improve its earnings mix. The source does not state the cause of the slower ordering momentum.
AI cooling pumps (technology pumps, 100 metric tons of water per hour)Walrus PumpDigiTimes Asia
Micron does not plan to commercialize 4F² DRAM, stating that the architecture offers limited benefits while adding cost and complexity; meanwhile, Chinese rival ChangXin Memory Technologies (CXMT) is advancing the technology. This is a planned statement from Micron and does not involve any realized price or production changes.
As AI inference and agent applications fuel demand for server CPUs, memory modules and connectivity chips, China's IC designers are expanding into high-speed interconnect technologies. Montage Technology expects its third-quarter 2026 profit to more than double on stronger DDR5 shipments (a company expectation, not a realized result). Shenzhen-based Techwinsemi is developing Compute Express Link (CXL) memory expansion controllers. The source does not state any further cause; together, these efforts highlight China's growing interest in AI server connectivity.
DDR5CXL memory expansion controllerMontage Technology, TechwinsemiDigiTimes Asia
Meta Platforms reported third-quarter results: for the quarter ended September 30, 2026, revenue rose 26% year on year to US$64.6 billion, and its core advertising business is still growing fast enough to carry one of the largest infrastructure programs in the technology industry (its AI build-out); meanwhile the operating margin fell to 20% from 40% a year earlier, with legal liabilities becoming a material cost line. The source does not state the cause.
Memory module maker GoldKey Technology posted record third-quarter 2026 profit, with quarterly net income topping NT$1 billion (approx. US$30.9 million) for the first time at NT$1.03 billion, up 6.2% quarter-over-quarter. However, the conversion of convertible bonds increased its share capital, pushing earnings per share down to NT$9.14 from NT$10.17 in the second quarter.
Persistent supply shortages have kept the niche memory market hot, with Elite Semiconductor Microelectronics Technology (ESMT) estimating that the structural supply gap exceeds 30%. The company expects tight supply and demand to continue through 2028 or longer, while price increases are set to continue in the fourth quarter of 2026 and are expected to support stronger operating performance in the fourth quarter than in the third quarter. These are company forecasts/estimates about the future, not achieved results; the source does not state any cause beyond the supply shortages.
niche memoryElite Semiconductor Microelectronics Technology (ESMT)DigiTimes AsiaPrice Movement
3M Chairman and CEO Bill Brown outlined the latest progress in the company's expanded beam optics (EBO) technology during its third-quarter earnings call, highlighting a contract manufacturing agreement with Taiwan's Largan Precision and the technology's potential US$2 billion market opportunity. The disclosure was made on the earnings call; the source does not state the specific terms or implementation timeline of the agreement.
Micron is reportedly sticking with its 6F² DRAM architecture rather than adopting 4F², even as Chinese rival CXMT advances the alternative design. According to Nikkei, Scott DeBoer, Micron's president and chief technology and products officer, said during a recent technology webinar that 4F² is not 'on the roadmap right now' after more than 20 years of evaluation; the company plans to extend its 6F² architecture while developing 3D DRAM as a longer-term alternative. DeBoer explained that DRAM bit density is primarily determined by capacitor pitch rather than cell architecture alone, and pointed to fundamental scaling limitations, greater manufacturing complexity, and higher costs associated with 4F². Roadmap details: the 1γ (1-gamma) node is already in high-volume manufacturing and will underpin products introduced over the next 12 months; the next node, 1δ (1-delta), is expected to enter volume production in the second half of 2027, targeting a bit-density improvement in the mid-20% range, and will support next-generation memory products including DDR6, LPDDR6, HBM5, and vertical HBM (vHBM); the 1ε (1-epsilon) node is being developed with wafer bonding to improve bit density and support AI applications; for the subsequent 1ζ (1-zeta) and 1η (1-eta) nodes, the company is exploring High-NA EUV, new materials, and other innovations. 3D DRAM is placed between the 1ζ and 1η nodes in the roadmap, but development is proceeding in parallel with planar DRAM, with adoption depending on cost, manufacturing complexity, and device performance. On products, Micron is preparing DDR6 and LPDDR6, targeting twice the bandwidth of DDR5 and a 35% improvement in power efficiency over LPDDR5 respectively, with greater efficiency gains at certain densities; the company also plans a 1TB RDIMM following its recent sampling of a 512GB DDR5 RDIMM. For AI applications, Micron is advancing vHBM, which stacks memory directly on processing chips to deliver substantially higher bandwidth, developing it alongside standard and custom HBM products, although thermal management remains a challenge; packaging efforts include hybrid bonding, taller HBM stacks, and improved cooling technologies. For NAND, Micron plans to ramp its Generation 11 (G11) technology in the second half of 2027; G11 targets twice the bit density of G9 NAND, 1.5 times the I/O speed, and lower data-transfer energy consumption, and will adopt wafer-on-wafer bonding and feature more than 400 layers.
At his keynote at the annual GTC 2026 Berlin conference on Oct. 21 local time, Nvidia CEO Jensen Huang said Nvidia has defined artificial intelligence as a new manufacturing industry that produces digital intelligence, or tokens, at scale, and unveiled a five-layer AI architecture dubbed the "Five-Layer Cake." The first layer is power and energy infrastructure that operates AI factories; the second comprises advanced computers and accelerated computing hardware that provide the foundation for AI processing; the third is AI factory infrastructure combining power and computing to produce tokens at scale, including neoclouds and communication networks; the fourth layer consists of AI models spanning various domains and scales, including language, biology, chemistry, physics, robotics and animation; the fifth layer comprises applications that integrate the resulting tokens into industries and enterprises. Huang said that, unlike conventional software tools, AI is a factory and a machine that produces intelligence on its own, and that the five-layer AI architecture connecting energy to applications would become the core infrastructure of the new industrial revolution. He emphasized that Europe must move beyond being merely a consumer of AI and become a producer of digital intelligence, urged European companies and governments to build independent production ecosystems rather than remain technology consumers, and said Europe has the capabilities to build the entire five-layer AI architecture independently. This is a strategic vision statement; the source contains no specific product, price or supply data.
On Oct. 21, Samsung Electro-Mechanics announced it had signed a strategic business partnership with Nvidia to supply semiconductor package substrates. The two companies will jointly invest to establish dedicated production facilities for artificial intelligence (AI) semiconductor package substrates at Samsung Electro-Mechanics' Sejong and Busan plants; the plan to expand package substrate production lines through customer-backed investment, under consideration since the first half of 2026, has taken shape through the Nvidia partnership. The products include flip-chip ball grid array (FC-BGA) substrates for AI computing chips and for network switches that enable high-speed connections between chips in data centers. Samsung Electro-Mechanics will supply next-generation substrates from its Korean production facilities under a multiyear arrangement beginning in 2026. Supply volumes are expected to grow at a double-digit annual rate starting in 2026, and by 2028 Nvidia-related production is expected to account for a significant share of the company's total capacity. The substrates will also embed passive components including multilayer ceramic capacitors (MLCCs) and silicon capacitors (Si-Caps), which will help control power noise generated during ultra-high-speed computing and maximize power efficiency. This is a planned/expected expansion; implementation remains to be carried out.
Song Jae-hyuk, chairman of the Korea Semiconductor Industry Association (KSIA) and president of Samsung Electronics, said at the 19th Semiconductor Day ceremony held at the Grand InterContinental Seoul Parnas in Gangnam, Seoul, on Oct. 21 that timely investment is the most important factor for the semiconductor industry. He called on the government to take proactive administrative measures to support companies in developing new technologies and investing at the right time through proactive infrastructure development, expedited permits and approvals, and bold, swift policy support. He noted that competition in semiconductor technology is intensifying between countries, with major countries fostering semiconductors as a national strategic industry, and that as the AI era gains momentum, advanced semiconductors offering high performance and high bandwidth are becoming increasingly important. He also pledged that the association will continue investing in advanced manufacturing facilities, next-generation technology development and talent cultivation. The article states South Korea achieved $10 billion in semiconductor exports in 1994, and cumulative shipments reached $340.3 billion through September 2026, roughly double the 2025 full-year exports of $173.4 billion. This year, 54 industry figures received government awards, with the Gold Tower Order of Industrial Service Merit going to Lee Jun-hyuk, chairman of Dongjin Semichem. This is a call/proposal, not an implemented policy.
semiconductorKorea Semiconductor Industry Association, Samsung Electronics and 3 totalThe ElecPolicy/Regulation
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Korea Semiconductor Industry Association, Samsung Electronics, Dongjin Semichem
PSMC's third-quarter revenue rose 23% sequentially and 80% annually to NT$21.3 billion, while net profit surged 98% and 338%, respectively, to NT$6.5 billion, with gross margin climbing 20 percentage points to 48%, driven by rising memory prices and tight foundry capacity. According to Liberty Times, PSMC President Martin Chu expects fourth-quarter revenue to grow by double digits sequentially as ASPs continue to rise; in the third quarter, completed memory wafers had ASPs more than 30% below those entering production during the same period, meaning recent price increases have yet to be fully reflected in revenue, with higher-priced wafers expected to contribute more in the fourth quarter. According to TechNews, global DRAM supply remains tight as major manufacturers shift capacity toward HBM and gradually exit specialty DRAM, keeping PSMC's specialty DRAM foundry prices elevated; PSMC is advancing its 1p DRAM collaboration with Micron, with a PDK due by the end of 2026, equipment arriving in 1Q27, and trial production starting in 2Q27. PSMC notes tight MLC NAND supply is driving demand for high-capacity SLC NAND, with the company shifting its SLC foundry platform to 24nm; AI servers require three to five times as much NOR Flash per system as conventional servers, and PSMC is the only NOR Flash foundry outside China. According to PSMC's earnings presentation, wafer input ASPs for its 8-inch and 12-inch logic foundry services rose 8–10% in the third quarter; with capacity constraints persisting, the company plans further price hikes of 10–20% in 2027 and is negotiating long-term agreements (LTAs) to secure pricing and volumes. PSMC has begun shipping 55nm BCD products with customers seeking three-year contracts; fully utilized 2026 foundry capacity is squeezing smartphone PMIC production, prompting major handset makers to seek 2027 capacity; 80% of 2027 MOSFET and IGBT capacity is already covered by LTAs; GaN products have entered small-volume wafer production pending final customer validation. IPD order visibility extends into 2028 with mass production underway on 8-inch and 12-inch wafers; WoW hybrid bonding small-scale trial production is underway with mass production targeted for 1H27. The Micron PWF project remains on schedule, with pilot line construction expected to finish by the end of 2026 and mass production planned for 4Q27.
memoryspecialty DRAMNAND FlashPowerchip Semiconductor Manufacturing Corporation (PSMC), MicronTrendForcePrice Movement
On 21 October 2026 (Wednesday), Intel announced that it had started installing production tools at its Fab 62 in Arizona, with the fab on track for mass production by late 2028; however, the company has not disclosed when it intends to begin high-volume production, the planned wafer processing capacity, the capital expenditures required to complete the facility, and it has not officially assigned Intel 14A to Fab 62 (Fab 62 remains unassigned, while Fab 52 has been designated for Intel 18A). Per Intel's manufacturing roadmap disclosed earlier this year, Fab 62 will be able to make chips on 18A, 18A-P, and 14A nodes. Intel also confirmed that it has integrated High-NA EUV lithography into high-volume manufacturing (HVM), used to produce select tiles for Panther Lake CPUs at its D1X fab in Oregon; Intel has not explicitly confirmed whether High-NA EUV scanners are currently used to produce the same circuits as Low-NA EUV machines. In addition, construction workers recently installed the first major structural truss at the first fab of the Ohio One complex in New Albany, Ohio, but Intel did not provide an updated construction schedule, disclose when the first fab is expected to begin operations, or reveal which process technology it will use or its estimated capacity. The source does not state the cause (this is a capacity expansion progress update, not a price or disruption event).
The source introduces the world's first 2,200-V PowiGaN technology, stating it enables higher power density, greater efficiency, and safer and simpler system architectures for next-generation high-voltage power systems serving AI data centers, EVs, photovoltaics, and HVDC infrastructure. The source does not state the cause, and no specific manufacturer, part number, date, price, or supply volume is mentioned.
Microchip's radiation-tolerant GaN point-of-load converter POL-05-20S-T delivers up to 20 A of continuous current to power FPGAs, MCUs and other digital loads in space. It uses a synchronous buck topology with current-mode control, an input voltage range of 4.75 V to 13.2 V, and an adjustable output of 0.7 V to 5 V. Its electrical parameters are specified before and after irradiation up to 50 krad(Si), and its single-event effects (SEE) have been characterized up to a linear energy transfer (LET) of 43 MeV·cm²/mg; it operates at full load over −55°C to +100°C. Housed in a 1.51×1.51×0.45-in. surface-mount package, it is now available in production quantities. The source does not state the cause (not an event-driven report).
GaN point-of-load converterGaN power HEMTsMicrochipEDN
NVIDIA announced plans with a group of supply chain partners to expand global manufacturing capacity to meet growing demand for its accelerated computing and full-stack AI factory platform. The partners include Amkor Technology, IBIDEN, King Yuan Electronics (KYEC), Samsung Electro-Mechanics, Siliconware Precision Industries (SPIL) and Unimicron Technology Corporation, with expansion of critical manufacturing capabilities across substrates, advanced packaging, testing and optical engines, covering both new and existing suppliers, to strengthen the resiliency and redundancy of NVIDIA's global supply chain. This is an announced expansion plan only; the source does not indicate the capacity changes have been implemented.
substratesadvanced packagingtestingNVIDIA, Amkor Technology and 7 totalTechPowerUpCapacity Change
According to ZDNet citing industry sources, Groq, the AI chip company that licensed its inference technology to NVIDIA, is reportedly considering 3D-stacked DRAM for its next-generation chips, a potential shift away from its SRAM-centric design that could significantly increase on-chip memory capacity; this remains a reported plan/rumor, not a confirmed implementation. The report indicates Groq is exploring 3DS (3D Stacked Memory), which uses through-silicon vias (TSVs) to vertically connect DRAM dies; while both 3DS and HBM rely on TSVs, HBM focuses on high data transfer speeds while 3DS aims to increase memory capacity while retaining conventional DRAM interfaces. The existing NVIDIA Groq 3 LPX is a rack-scale AI inference accelerator designed for low-latency, large-context workloads on the Vera Rubin platform; according to NVIDIA, each Groq 3 LPU integrates 500MB of SRAM with 150TB/s of on-chip memory bandwidth, while a full LPX rack combines 256 LPUs to deliver 128GB of SRAM and 40PB/s of aggregate SRAM bandwidth; according to the company, each rack provides 12TB of DDR5 memory alongside 128GB of SRAM. According to 36Kr citing d-Matrix CEO Sid Sheth, SRAM capacity increases by only around 10–20% every two years while AI model sizes could double every six to nine months, making it increasingly difficult for SRAM alone to meet growing demands for memory capacity and bandwidth. On manufacturing, according to Seoul Economic Daily, Samsung Foundry produces NVIDIA's Groq 3 LPU using its 4nm process at its Pyeongtaek facility; Samsung executives said in June that the company was discussing foundry cooperation with NVIDIA on the next-generation Groq LPU, and TSMC Chairman C.C. Wei said during the company's April earnings call that TSMC was working with customers on next-generation LPU development. Separately, Cerebras, another AI chipmaker that relies heavily on SRAM, is also pursuing 3D-stacked DRAM; according to the company, its future CS-6 system will integrate stacked DRAM with wafer-scale SRAM and compute to significantly expand memory capacity while preserving fast data access.
SRAM3D-stacked DRAM (3DS)HBMGroq, NVIDIA and 6 totalTrendForce
At SEMICON West 2026, under the theme "Optical Integration for the Next Generation of AI," NVIDIA presented its next-generation co-packaged optics (CPO) technology, including an optics-on-interposer (OOI) prototype that moves optical engines from the organic package substrate onto the silicon interposer carrying the computing chips; according to The Elec, this eliminates the organic substrate from the electrical signal path, allowing signals to travel through shorter, fine-pitch interposer connections that could increase bandwidth density and reduce power consumption. NVIDIA also demonstrated DWDM technology that, according to Wccftech, combines eight wavelengths operating at up to 32 Gb/s each, delivering an aggregate bandwidth of 256 Gb/s per fiber. Both technologies remain in the research stage with no commercialization timeline announced, and NVIDIA said it is evaluating them for potential future products. Looking ahead, NVIDIA plans to extend optical interconnects with its Kyber NVL1152 architecture, which will connect eight racks into a single 1,152-GPU NVLink domain and support the Feynman platform, which Wccftech says is expected to arrive in 2028. On existing products, in May 2026 NVIDIA announced that its Spectrum-X Ethernet Photonics switches had entered full production, integrating 200Gb/s SerDes with CPO technology for the Vera Rubin platform, with CoreWeave, Lambda, and Oracle Cloud Infrastructure among early adopters; its manufacturing ecosystem includes TSMC for silicon photonics fabrication, SPIL for chip-scale packaging, assembly, and testing, TFC for laser die packaging and reliability validation, and Foxconn for integrating Spectrum-X Photonics switches into complete networking systems, plus Coherent, Lumentum, and Sumitomo Electric for external laser source modules, Corning, Senko, and Browave for optical fibers and related components, and Fabrinet for cooling and final testing.