NuAxiSemiconductor trade intelligence

Micron details ambitious DRAM and NAND roadmap — 3D NAND, High-NA EUV, new materials, and custom silicon makes a comeback

What happened

Micron disclosed its DRAM and NAND roadmaps for the coming years (plans, not yet realized results). On DRAM, Micron decided to abandon plans to produce DRAM with 4F² memory cells — unlike rivals CXMT, Samsung, and SK hynix — citing, per the source, the lack of a viable scaling path beyond where Micron is today; its roadmap instead includes wafer bonding, High-NA EUV lithography, new materials, and eventually 3D DRAM, while continuing DRAM development based on 6F² cells. Micron's current 1γ (1-gamma) process is in high-volume manufacturing and is its first DRAM node to use EUV. The next-generation 1δ (1-delta) process is in the yield ramp stage, scheduled to enter mass production in the second half of 2027, with expected bit density increase of mid-20% compared to 1γ; Micron plans to manufacture 1δ DRAM in the U.S. and use it for next-generation DDR, LPDDR, graphics memory, HBM5, vHBM, and vEIM products. The 1ε process (using wafer bonding) is under development with no announced production schedule; the ζÅ node is in early development and will introduce High-NA EUV with no disclosed production timing and will not arrive until at least 2030 (Samsung and SK hynix plan High-NA EUV adoption at their DRAM fabs in 2028); the ηÅ process is in the pathfinding stage. Micron is developing two generations of 3D DRAM (3D1 and 3D2) to be introduced only when competitive in cost and performance, with no disclosed architectures, layer counts, or density targets; only the 1δ process has a firm production window (2H 2027). On custom memory, starting with HBM4E Micron will offer both standard and custom HBM, followed by custom HBM5E, vHBM, and vEIM; 1st-generation vEIM targets HBM4-like 2 TB/s bandwidth with less than 1 picojoule per bit transfer energy. Micron is collaborating with Meta to optimize LPDDR6 for data center applications, expecting LPDDR6 to reduce power consumption by approximately 35% compared to LPDDR5, and plans to develop DDR6 targeting 2X DDR5 bandwidth with major customers. Micron expects its CMOS logic performance to increase more than 10X between 2020 and 2030. On NAND, the G11 (N170) 3D NAND plans to increase active memory layers from 276 to more than 400, adopt wafer-on-wafer bonding, and is expected to double bit density versus G9 (N160) (presumably from 21 Gb/mm² to 42 Gb/mm² for 3D TLC), target a 50% I/O speed increase versus G9 (implying approximately 5,400 MT/s), and reduce data transfer energy consumption by more than 25% per bit, with mass production planned for the second half of 2027; beyond G11, Micron will rely on new materials and XYZ scaling. Micron is also developing High-IOPS AI NAND (SLC-based designs; products of approximately 25 million to 100 million IOPS over the next couple of years) and High-Bandwidth AI NAND (TSV-stacked NAND with a logic base die), plus conventional SSD plans with capacities up to 512 TB. All production and performance figures are company plans or expectations, not achieved results.