Part 2. zHBM: Next-Generation Memory for the Data Movement Era

What happened

In a technical explainer, Samsung states that zHBM, currently under development, is a next-generation AI memory architecture designed around AI inference, reasoning, long-context processing and agentic AI workloads that place greater demands on memory through more generated tokens and larger KV caches. Moving beyond conventional HBM architectures in which memory sits beside the AI chip, zHBM directly stacks memory on the processor. The article says zHBM uses direct 3D integration and a Distributed I/O architecture to create shorter, denser connections intended to deliver high bandwidth with greater energy efficiency; core technologies include Wafer-on-Wafer (WoW) stacking combined with Hybrid Copper Bonding (HCB) for direct copper-to-copper connections at fine pitches, and reduced size and pitch of Through Silicon Vias (TSVs) for higher interconnect density, with shorter interconnects lowering data-transfer energy. The article notes that direct stacking creates new thermal challenges, as heat generated by the processor may need to pass through the memory stack, and that Samsung is exploring stack-height optimization; it emphasizes co-design and co-optimization of memory with the AI chip from early development stages and aims to work with customers and ecosystem partners on zHBM solutions tailored to their AI chips' performance, power, thermal and architectural requirements. The article is informational only, with no specific timeline, capacity or pricing figures and no statement of market supply-demand conditions.

Impact and signal

Affected components and suppliers

Source and time

Source: Samsung Semiconductor Newsroom · 10/28/2026 · View original source