NuAxi Stream - Real-Time Semiconductor Intelligence

Mon, Oct 26

04:49Impact score 20
Silicon Photonic Modulator Reaches 200 Gb/s PAM4 With Reduced DSP (Science Tokyo, Yokohama, AIST, PETRA)
Researchers from Institute of Science Tokyo, Yokohama National University, AIST, and the Photonics Electronics Technology Research Association (PETRA) published a technical paper titled “Reduced-DSP 200G/λ Low-Voltage Slow-Light Silicon Modulator Enabled by Built-In EO Equalizer.” The abstract excerpt states that multi-Tb/s optical interconnects for artificial intelligence data centers necessitate high-speed, energy-efficient, and compact transceivers, but that conventional silicon Mach-Zehnder modulators have related limitations (the excerpt is truncated with an ellipsis). The research achieved a reduced-DSP 200G/λ low-voltage slow-light silicon modulator with a built-in EO equalizer, reaching 200 Gb/s PAM4. This is a published research paper and technology-advancement background item, not a price movement or supply-demand event; the source does not state any cause or commercialization timeline.
silicon photonic modulatorsilicon Mach-Zehnder modulatorInstitute of Science Tokyo, Yokohama National University and 4 totalSemiconductor Engineering

Sun, Oct 25

21:00Impact score 10
CEO Interview with Lisa Spelman of Cornelis
This is an interview with Lisa Spelman, CEO of Cornelis. She brings more than 20 years of experience across AI, cloud, enterprise infrastructure, data center operations, product strategy, and go-to-market leadership; before joining Cornelis she served as Corporate Vice President at Intel, where she led the Xeon Products and Solutions business within the Data Center & AI Group. At Cornelis she focuses on improving system utilization and reducing networking bottlenecks for AI infrastructure. The interview states: Cornelis is working on the third generation of its high-performance networking platform, with more than 50 OEM and ODM design wins; it is deployed in over 500 datacenters, including new large-scale deployments at Lawrence Livermore National Lab and the Texas Advanced Computing Center; and this month it announced the Active Compute Fabric, which adds programmable RISC-V cores at every hop across every NIC and switch to accelerate collectives, KV cache, and MoE routing, built on open standards (UALink and ESUN for scale-up, Ultra Ethernet for scale-out). The source does not state the cause; this is a background interview with no reported price, capacity, or supply-demand change.
SuperNICsswitcheshigh-performance networking platformCornelisSemiWiki
07:26Impact score 58
RT NEWS: #Micron says #AI cut data center #SSD controller design time by 50% and product development time by 60% vs. the prior generation, and plans $...
Micron said AI cut data center SSD controller design time by 50% and product development time by 60% versus the prior generation. Micron also plans to invest $10B over the next decade in Micron Research Labs, its first dedicated U.S. memory research hub. The investment is stated as a plan; the source does not specify a construction timetable or implementation details.
data center SSD controllerMicronTrendForce Official (Market Data)

Sat, Oct 24

00:34Impact score 55
Vertical Semiconductor gains $73m in US CHIPS Act funding
Vertical Semiconductor signed a letter of intent with the US Department of Commerce's CHIPS Research and Development Office (CRDO) to receive up to $73m in federal incentives under the CHIPS and Science Act.
Vertical SemiconductorSemiconductor TodayPolicy/Regulation
00:00Impact score 30
Delta Unveils SST-Based DC Power System for AI Data Centers
Delta is showcasing microgrid solutions for AI factories, high-performance computing (HPC) data centers, and smart manufacturing at Energy Taiwan 2026, held October 14 to 16 at Taipei Nangang Exhibition Center, Hall 1, 4F, Booth M0319a. Its prefabricated DC power system based on solid-state transformers (SSTs) uses a containerized architecture integrating SSTs, DC/DC converters, and control equipment, reduces the number of power conversion stages, and achieves SST energy efficiency of up to 98.5%; according to Delta, its implementation can improve grid-to-chip energy efficiency in AI data centers by 4–5%. The system can incorporate high-C-rate batteries to respond to rapid AI workload variations, providing millisecond-level power support, and its modular, prefabricated design can potentially shorten deployment time by up to 50%, with an architecture supporting future capacity expansion as computing demand increases. Delta is also presenting solid oxide fuel cell (SOFC) technology for distributed power generation, with overall system efficiency of up to 85% when heat recovery is included; Delta plans to begin trial production of its SOFC solution by the end of 2026. The exhibition also includes EnergiQ, a digital energy management platform developed by Delta's ESG Consulting Office and built around the ISO 50001 methodology, plus expert presentations involving Taiwan's Industrial Technology Research Institute, Taiwan Institute of Economic Research, and Delta's smart energy and microgrid teams.
solid-state transformers (SSTs)DC/DC converterssolid oxide fuel cell (SOFC) technologyDeltaPower Electronics News

Fri, Oct 23

21:00Impact score 55
US to provide up to $389 million in CHIPS awards to 4 firms
The US Department of Commerce announced the signing of four letters of intent to provide up to USD 389 million in federal R&D awards under the CHIPS and Science Act (reported October 23, 2026). Under the final awards, each company will conduct R&D to address critical projects spanning power semiconductor devices, modules and materials essential to the semiconductor supply chain. Helion will receive up to USD 175 million to develop, scale and establish domestic capabilities in high-voltage power semiconductors and advanced energy power modules for high-peak-current pulsed-power applications in fusion power generation. Commonwealth Fusion Systems will receive up to USD 85 million for R&D on semiconductors for radio-frequency plasma heating, power electronics, embedded electronics for fusion diagnostics, and radiation-hardened electronics. Vertical Semiconductor will receive up to USD 73 million to advance its vertical GaN power semiconductors, enabling more efficient and compact power delivery for advanced computing. Sibelco will receive up to USD 56 million to develop next-generation purification and finishing technologies for ultra-high-purity quartz used in crystal growth crucibles and other hardware. This is an announcement of signed letters of intent for R&D funding, a policy development to be watched for any price impact.
power semiconductor devicespower semiconductor modulesvertical GaN power semiconductorsHelion, Commonwealth Fusion Systems and 4 totalEvertiqPolicy/Regulation
15:17Impact score 60
YMTC to Start Mass Production of LPDDR5X with 9,600 MT/s Speed
According to Counterpoint Research, YMTC, known primarily as a NAND Flash manufacturer, has been producing about 5,000 wafers per month of 16 Gb LPDDR5X DRAM running at 7,500 MT/s at its Fab 2 since October 2025. The company is now preparing to begin volume production of LPDDR5X memory with speeds of 9,600 MT/s at its Fab 3, using Vertical Channel Transistor (VCT) 4F² cell structure technology. The volume production remains in the preparation stage and is a planned event.
LPDDR5X DRAM16 Gb LPDDR5X DRAMYMTCTechPowerUpCapacity Change
13:13Impact score 60
Washington takes stake in fusion company
Washington took a 1.13% stake in Helion for a $175 million Chips Act grant and $50 million private investment, totaling $225 million. The award supports U.S. development and transition to manufacturing next-generation, high-voltage semiconductors, with $100 million for R&D in Everett, Washington, and $80 million for tooling in Burlington, Vermont.
next-generation, high-voltage semiconductorsadvanced semiconductorspower module manufacturing capabilityHelionElectronics WeeklyPolicy/Regulation
11:56Impact score 0
US signs up to US$389 million in CHIPS R&D deals for power chips and fusion
The US Department of Commerce signed letters of intent with four companies on October 22, 2026, to provide up to US$389 million in federal research and development awards under the CHIPS and Science Act, targeting the semiconductors and materials used to control, convert, and deliver power.
semiconductors and materials used to control, convert, and deliver powerDigiTimes AsiaPolicy/Regulation
11:29Impact score 0
Mounting R&D and memory costs push Huawei to borrow US$2.3B from six Chinese banks
Huawei Technologies secured a seven-year, CNY15 billion offshore yuan loan from six Chinese banks as rising research spending and memory costs weigh on its cash flow. The financing is Huawei's first offshore syndicated borrowing since 2020, Bloomberg reported, citing a person familiar with the matter.
memory costsHuawei TechnologiesDigiTimes Asia
08:35Impact score 60
Lam Research sees WFE topping US$200 billion in 2027
Lam Research reported third-quarter 2026 revenue of US$8.2 billion, up 22% quarter-over-quarter, and forecast fourth-quarter revenue of US$8.6 billion, plus or minus US$400 million. The company expects the wafer fabrication equipment (WFE) market to reach the mid-US$150 billion range in 2026 and initially forecasts more than US$200 billion in 2027, with percentage growth led by DRAM. The 2026 and 2027 figures are forecasts, not achieved results.
wafer fabrication equipment (WFE)DRAMLam ResearchDigiTimes Asia
08:26Impact score 55
AMEC ships first Primo Domingo selective etching system, targeting critical gaps in China's advanced 3D chipmaking
China's Advanced Micro-Fabrication Equipment (AMEC) has shipped the first unit of its Primo Domingo high-selectivity vapor-phase etching system to a major domestic semiconductor research and manufacturing customer, marking a step forward in China's efforts to develop indigenous equipment for next-generation 3D chips and targeting critical gaps in China's advanced 3D chipmaking.
selective etching equipmentAdvanced Micro-Fabrication Equipment (AMEC)DigiTimes Asia
06:51Impact score 60
Merck Expands Molybdenum Use to DRAM and Logic Chips
Germany's Merck plans to expand the use of molybdenum dioxide dichloride (MoO₂Cl₂) precursors from NAND flash memory to DRAM and logic semiconductors. Bing Han, senior vice president of the Thin Film Materials business at Merck Electronics, said at a press conference at Sono Felice Samsung in Gangnam on Oct. 21 that as device structures shrink, conductivity issues with copper and tungsten will drive greater adoption of molybdenum. Merck has established a molybdenum precursor production facility in Eumseong, North Chungcheong Province, which will be integrated with its CHEMKEEPER Vapor 200 materials delivery systems made at its Ansan plant and offered as a turnkey solution. The expansion uses land near an existing plant of M Chemicals, which Merck acquired in 2023; the site previously produced hafnium-based high-k dielectric precursors, construction began in 2024, and the facility was prepared for operation within two years. Han said Merck is planning production capacity sufficient to meet all demand from Korean customers, but the company did not disclose specific production capacity or investment figures, and it plans to eventually expand support beyond Korea to customers across Asia. As background: Samsung Electronics began using molybdenum in its 200-layer-class NAND in 2024, and SK hynix has replaced some word-line materials with molybdenum in its 300-layer-class NAND; Lam Research, Tokyo Electron and Applied Materials are among the suppliers of molybdenum deposition equipment. Hein said Merck is reviewing production capacity with customers in preparation for semiconductor materials consumption potentially doubling within the next five years.
NAND flash memoryDRAMlogic semiconductorsMerck, Merck Electronics and 4 totalThe ElecCapacity Change
06:49Impact score 55
Mobilint to Develop Computing Platform for Physical AI
On Oct. 22, Mobilint said it will develop a computing platform for physical AI applications, including humanoid robots. The company has been selected as the lead research organization for a project to develop on-device AI accelerators for humanoids, part of the Ministry of Trade, Industry and Resources' K-On-Device AI Semiconductor Technology Development Program, overseen by the Korea Planning & Evaluation Institute of Industrial Technology (KEIT). Mobilint will design a neural processing unit (NPU) to accelerate AI computing for humanoids, ultimately aims to develop an accelerator module that can be installed directly in robots, and will also develop a software environment for optimizing AI models. The completed platform will undergo phased validation and improvement through integration with LG Electronics' humanoid system designed for everyday environments. Mobilint plans to expand the technology beyond humanoids into other physical AI applications, including service robots, autonomous mobile robots (AMRs), smart home appliances and AI cameras.
on-device AI acceleratorneural processing unit (NPU)accelerator moduleMobilint, LG ElectronicsThe Elec
06:49Impact score 40
HPSP Adopts Co-CEO Structure
On Oct. 22, HPSP held an extraordinary shareholders' meeting at its headquarters in Hwaseong, Gyeonggi Province, where shareholders approved Kim Jae-hyun as new CEO with 96.3% voting in favor and 3.7% voting against or abstaining; his term is two years and five months. Kim Jae-hyun, former CEO of Hanwha Semitech, will serve alongside incumbent CEO Kevin Ki-doo Lee under a co-CEO structure. The source does not state the cause. Kim previously worked at Applied Materials Korea, Samsung Electronics, Lam Research and Wonik IPS, spanning front-end and back-end semiconductor equipment, and served as CEO of Hanwha Semitech from Nov. 2, 2025. Shareholders also approved amendments to the articles of incorporation concerning strategic investments and acquisitions of shares in other companies, primarily establishing a clearer basis for issuing new shares to third parties for business purposes; the proposal passed with 98.1% in favor and 1.9% against or abstaining. An HPSP official said the company is considering options including mergers and acquisitions (M&A) to strengthen its capabilities in high-pressure gases used in HPA and related gas technologies, and that the amendments establish an institutional framework for future M&A transactions or acquisition financing; HPSP has approximately 250 billion won in cash equivalents and short-term financial assets available for potential M&A and related investments. HPSP is the global leader in high-pressure hydrogen annealing (HPA) equipment, with customers including major memory semiconductor manufacturers and foundries worldwide, and plans to accelerate semiconductor equipment R&D under Kim's leadership.
high-pressure hydrogen annealing (HPA) equipmentHPSPThe Elec
03:57Impact score 60
Micron Walks Away From 4F² DRAM After Two Decades of Research, Bets on 3D DRAM Instead
Micron has decided not to bring 4F² DRAM to market, even though it says it invented the cell design and has been researching it for around two decades. Scott DeBoer, Micron's President and Chief Technology and Products Officer, shared the decision during the company's technology webinar on October 21. On paper, 4F² uses vertical channel transistors to shrink each memory cell's footprint by about a third compared with the 6F² layout used in today's DRAM; however, DeBoer argued that real-world density is limited by how closely the capacitors can be packed, not by the cell's footprint, calling the density advantage over 6F² "a bit of a myth." He also said 4F² can be built, but at a higher cost and complexity, and that it runs into fundamental scaling problems at leading-edge nodes, which points toward 3D DRAM. This puts Micron at odds with its rivals: Samsung and SK hynix are both developing 4F² designs, and China's CXMT says its first 4F² product will be a server DDR5 RDIMM due by the end of this year. Micron will keep scaling 6F² instead, with its 1-delta node set to ramp in Boise, Idaho, in the second half of 2027 and the 1-epsilon node after it moving to wafer bonding. 3D DRAM is being developed as a parallel path, but there's no timeline yet, and Micron says it will only switch once the economics make sense. It is a risky bet if rivals manage to make 4F² cheap at scale, especially with memory supply expected to get even tighter in 2027 and 2028, per Micron's own estimates.
4F² DRAM6F² DRAM3D DRAMMicron, Samsung and 4 totalTechPowerUpEOL/Discontinuation
01:00Impact score 0
From Sequential R&D to Trusted Co-Innovation: The EPIC Model for Semiconductor Innovation
On October 12, 2026, Applied Materials President and CEO Gary Dickerson delivered a keynote at the unveiling of the EPIC Center in Sunnyvale, CA, advocating for a shift from sequential R&D to trusted co-innovation. The EPIC Center is intended to bring Applied Materials and industry partners together to work on next-generation materials, processes, and equipment.
next-generation materials, processes and equipmentApplied MaterialsSemiWikiPartnership/M&A

Thu, Oct 22

22:48Impact score 62
Micron skipping planned NAND generation
At a technology and product webinar held on October 21 on its Investor Relations website, Micron announced it is skipping a planned NAND generation, accelerating its 3D NAND technology roadmap to provide additional die capacity, speed and energy efficiency faster. According to Blocks & Files, published Thursday 22 Oct 2026 at 15:48 UTC, Micron is currently shipping G9, its ninth generation with 276 layers; the first product using this tech, the 2650 client SSD, launched in July 2024. President and Chief Technology and Products Officer Scott DeBoer said Micron will go from Gen 9 directly to Gen 11, describing the memory as optimized for the AI products of the future. Compared to G9, G11 has twice the bit density, up to 1.5x higher I/O speed and needs 25 percent less energy to transfer a bit; it is based on wafer-on-wafer bonding technology, will exceed 400 layers, and will ramp in the second half of next year, with more specifics promised next year closer to launch. The publication's bootnote notes that Gen 8 (planned 300+ layers, branded G10 externally) was abandoned in Oct 2026, with Gen 9 (planned 400+ layers) branded G11 externally in Oct 2026. DeBoer also outlined future product directions possibly using G11: a high-IOPS SLC-based, small-block AI-class NAND (in the 25–100 million IOPS area) and a high-bandwidth AI-class NAND with TSV-connected stacked layers placed near the accelerator, with next-generation SSDs holding up to 512 TB. Additionally, per BNP Paribas analyst Karl Ackerman, Micron's HBM4 36GB 12-high entered high-volume manufacturing in March 2026, HBM4E is currently sampling with key customers, with targets of HBM4E HVM in 2027, HBM5 in 2028, HBM5E in 2029 and HBM6 in 2030, plus newly announced vHBM and vEIM lines targeted for volume production in 2028. As to the cause, Micron says the skip is intended to provide additional die capacity, speed and energy efficiency faster, with G11 optimized for future AI products; the publication separately offers its own opinion that the generation skipping is marketing-based and a response to Samsung, SK hynix and Sandisk/Kioxia generation naming, which is media commentary rather than a Micron statement.
3D NANDNANDSSDMicronBlocks & FilesEOL/Discontinuation
21:52Impact score 10
Robotiq Launches the 2FC Physical AI Gripper
Robotiq today launched the 2FC physical AI gripper, a production-ready adaptive gripper with tactile sensing and embedded intelligence. Pre-orders open today, with shipping planned in Q1 2027 (shipping is planned, not yet realized). The product builds on Robotiq's 2F adaptive gripper, a platform with more than 30,000 deployed worldwide, and adds tactile sensing, compute at the wrist (the AI Hub) and Contact Core, Robotiq's software for physical AI. The gripper captures pressure, vibration, proprioception, force, position and current, synchronized at millisecond level, and currently runs grasp skills locally and in real time, including grasp quality assessment, incipient slip detection, object pose estimation, object centering and advanced grip check. The gripper is rated for 2 million cycles and is underactuated for both parallel and encompassing grasps; existing owners of Robotiq's 2F grippers can add TSF tactile sensors and the AI Hub to upgrade rather than replacing their gripper.
RobotiqEE Journal
20:00Impact score 85
Micron pulls the plug on future 4F² DRAM after two decades of research in dramatic shift
On 22 October 2026, Micron announced it will abandon future 4F² DRAM after roughly two decades of research. The company says the architecture offers no meaningful density advantages, increases manufacturing complexity and costs, and has fundamental scaling limitations; CTO Scott DeBoer said capacitor pitch, not nominal transistor area, determines DRAM bit density, and that 4F² has no sustainable scaling path beyond a certain point, with 3D DRAM ultimately coming in instead. Micron acknowledges 4F² is technically feasible and that it has manufactured experimental devices based on the architecture. A 4F² cell theoretically occupies about 33% less area than a 6F² cell and could theoretically increase memory cells per wafer by 50%, but Micron argues these theoretical advantages do not necessarily translate into higher density in practice. Micron plans to continue scaling conventional 6F² DRAM by reducing capacitor pitch and shrinking process nodes; its upcoming 1δ process technology is scheduled to enter volume production in the second half of 2027 with a mid-20% improvement in bit density compared with its predecessor, and Micron plans to adopt High-NA EUV lithography for future DRAM generations. The company is also developing multiple generations of 3D DRAM production nodes but has not disclosed when the new architecture will enter commercial production. According to TechInsights, both Samsung and SK hynix still have 4F² memory cells in their roadmaps.
DRAMMicronTom's HardwareEOL/Discontinuation

Analog	$0.68	−5.9%
Connector	$0.75	+0.2%
CPU	$386.74	−21.3%
DDR4	$88.40	−0.2%
DDR52026-W13	$14.89	−11.2%
GPU	$478.20	+8.2%
MCU	$0.68	−61.7%Unusual
MLCC	$0.01	+54.0%Unusual
MOSFET	$0.12	−82.8%Unusual
PMIC2026-W13	$0.44	−12.5%
SSD/HDD	$288.43	n/a

NuAxi Stream - Real-Time Semiconductor Intelligence

Mon, Oct 26

Silicon Photonic Modulator Reaches 200 Gb/s PAM4 With Reduced DSP (Science Tokyo, Yokohama, AIST, PETRA)

Sun, Oct 25

CEO Interview with Lisa Spelman of Cornelis

RT NEWS: #Micron says #AI cut data center #SSD controller design time by 50% and product development time by 60% vs. the prior generation, and plans $...

Sat, Oct 24

Vertical Semiconductor gains $73m in US CHIPS Act funding

Delta Unveils SST-Based DC Power System for AI Data Centers

Fri, Oct 23

US to provide up to $389 million in CHIPS awards to 4 firms

YMTC to Start Mass Production of LPDDR5X with 9,600 MT/s Speed

Washington takes stake in fusion company

US signs up to US$389 million in CHIPS R&D deals for power chips and fusion

Mounting R&D and memory costs push Huawei to borrow US$2.3B from six Chinese banks

Lam Research sees WFE topping US$200 billion in 2027

AMEC ships first Primo Domingo selective etching system, targeting critical gaps in China's advanced 3D chipmaking

Merck Expands Molybdenum Use to DRAM and Logic Chips

Mobilint to Develop Computing Platform for Physical AI

HPSP Adopts Co-CEO Structure

Micron Walks Away From 4F² DRAM After Two Decades of Research, Bets on 3D DRAM Instead

From Sequential R&D to Trusted Co-Innovation: The EPIC Model for Semiconductor Innovation

Thu, Oct 22

Micron skipping planned NAND generation

Robotiq Launches the 2FC Physical AI Gripper

Micron pulls the plug on future 4F² DRAM after two decades of research in dramatic shift

Chip Teardown Lab2 opened

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