Inside Navitas’ Claros IVR: How Digital Control Scales Power Delivery to Thousands of Amps

What happened

According to the article, Navitas closed the Claros acquisition in early October 2026, calling it a defining step in the Navitas 2.0 transformation, and formed a new IVR business unit headed by Dan Kultran (Claros' former co-founder and CEO) as VP and GM. In the context of a recent webinar and an exclusive interview with Kultran, the article details the Claros IVR technology: the basic unit is a 10-A building block that can be combined into 40-A or 160-A chips; the 40-A chip, integrating all passive components, measures 3.3 × 3.6 mm and delivers a current density of about 3.4 A/mm²; via the PowerArray architecture, a single master coordinates up to 64 chips in one voltage domain, delivering ~2,500 A with 40-A chips or ~10,000 A with 160-A chips; a host can address up to 26 masters, with a theoretical ceiling of ~66,500 A for 40-A chips and ~266,000 A for 160-A chips, though Kultran noted customers' voltage domains actually draw roughly 700 A to 1,200 A each. Each Claros IVR chip embeds its own controller and shares current digitally over its own high-speed bus (each die senses current with SenseFETs and digitizes it with an on-die ADC). Input is 3.3 V nominal with output typically 0.8 V and below, a ratio of a little over 4:1, climbing to about 5.5:1 as customers move to core voltages near 0.6 V; Navitas is already developing a version that takes 6 V directly down to the core, planned to reach 6:1 for a 1-V core. The technology ships as P-IVR (beneath the processor) and E-IVR (embedded in the processor substrate). CEO Chris Allexandre said during the webinar that the identified 2030 TAM expands from the original $3.5 billion GaN and SiC base to more than $8 billion, including new JFET technology and Claros IVR. The article also cites projected GPU power rising from ~1.4 kW in 2025 to 4.4 kW in 2028 and well above 10 kW by 2030 and beyond, and an 800-V-to-6-V reference design released by Navitas and Microchip in October 2026, building on the power delivery board (PDB) unveiled at NVIDIA GTC in March.

Impact and signal

Affected components and suppliers

Source and time

Source: Power Electronics News · 11/5/2026 · View original source