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[News] Qualcomm Completes HBC Validation, Claims 5×+ HBM4 Bandwidth Efficiency; AI250 Sampling in 1H27

What happened

Qualcomm has completed initial hardware validation of its first-generation High Bandwidth Compute (HBC) technology, marking a key step toward commercialization; according to ServeTheHome, the company successfully tested HBC's memory read-write and near-memory computing capabilities. According to ServeTheHome, Qualcomm measured bandwidth-per-watt efficiency at more than five times that of HBM4, based on a comparison with HBM4 specifications, and also reported 18 times the bandwidth of external LPDDR5X, without disclosing specific bandwidth figures. HBC stacks LPDDR memory directly on a compute die and uses LPDDR5X DRAM dies instead of the specialized DRAM dies used in HBM, aiming to reduce data movement and power consumption and lower packaging costs, potentially enabling less expensive packaging such as conventional 2D organic substrates; HBC stacks are expected to offer greater memory capacity than current HBM4 implementations, though Qualcomm has yet to disclose final performance specifications. The technology is set to debut in Qualcomm's Dragonfly AI250 accelerator, scheduled to begin sampling in the first half of 2027. Samsung Electronics and SK hynix have reportedly been working with Qualcomm on HBC commercialization, while TSMC is expected to support technology integration and advanced packaging; however, the companies have yet to publicly confirm specific production arrangements. Qualcomm also plans to extend HBC to its next-generation Dragonfly AI300 accelerator; per the company's June announcement, AI300 will feature second-generation HBC technology, targeting 54 times the effective memory bandwidth of the LPDDR5X-based AI200, with sampling expected in 2028.