NuAxiSemiconductor trade intelligence

TSMC’s Patent and the Harsh Realities of 3D DRAM Competition

What happened

TSMC's patent disclosures involving vertical DRAM raise the question of whether the foundry could eventually challenge established memory makers. The source notes that US20220359529A1, published in November 2022, describes a vertical-channel transistor integrated with a hybrid trench-and-stacked capacitor, while another application filed in May 2022 and published as US20230240066A1 places a capacitor directly above a vertical gate-all-around transistor. The article stresses these are technical explorations that should not be merged into a single architecture or treated as product announcements, and do not establish TSMC's production readiness, investment commitment, or intention to sell commodity DRAM; plausible uses (embedded memory, logic-memory integration, or future customer requirements) remain an inference rather than a disclosed commercial strategy. SK hynix has publicly identified both a 4F² vertical-gate platform and 3D DRAM as future directions, though these are related but distinct concepts. The article lists three obstacles for 3D DRAM: electrical control, capacitor integration, and manufacturing economics, concluding that competition will be decided by turning promising structures into dependable products at competitive cost. The source states no price movement or supply change.