ML-Based Power Models for CPUs. Innovation in Verification

What happened

A research commentary article discusses the 2023 paper 'Machine Learning-Based Microarchitecture-Level Power Modeling of CPUs', published in the IEEE Transactions on Computers with authors from UT Austin plus Hyperstone and U Stuttgart in Germany; the paper has 18 citations and extends a 2021 learning-based power modeling paper (which covered fixed function accelerators) to programmable in-order and out-of-order CPUs, with the learning method based on DNNs. The authors train decision-tree models to predict power for a single clock cycle on low level CPU building blocks such as fetch, decode, and load-store, trained using golden power data from a post-P&R gate-level netlist and simulation traces, then assemble the models hierarchically to construct a cycle-accurate power profile from a cycle-accurate micro-architectural simulation trace of the complete design. Results on two open source designs (a simple in-order CPU and the complex out-of-order CPU BOOM), implemented on an open source 45nm process and library, show that with only 20k cycles of training data using 8 very simple test programs (quick sort, Towers of Hanoi, Dhrystone, ...), power estimation for BOOM on the CoreMark benchmark has an average error in any clock cycle of less than 4%; at the resolution of individual building blocks, 80% of the blocks are within a 15% error in any clock cycle; and the runtime overhead of processing the decision trees is negligible. The commentary also cites that gate-level reference power estimation of the BOOM processor (approx. 460K standard cells) took a total of 40-65 hours running at 2-3 cycles/s versus 7-9 hours using the learned models and Verilator-based simulation, a speedup of roughly 5-9x; that the 3.6% MAE on CoreMark is normalized to the average power of the entire CPU and does not mean power is predicted within 3.6% in every cycle, with accuracy varying strongly across blocks (ALU 15% MAE, issue unit 18%, memory issue unit 23%); and that the decision trees are calibrated against a particular synthesized and placed-and-routed design, with the authors providing no evidence that characterized blocks preserve accuracy across different configurations, so applicability to design-space exploration remains unclear.

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Source: SemiWiki · 10/29/2026 · View original source