Wilson Survey Signals Need for New Understanding of Verification Success

What happened

Siemens has again sponsored a Wilson-led survey on the state of (functional) verification in the industry, and Harry Foster (Chief Scientist, Verification at Siemens) has condensed his major takeaways from the report. The survey shows an apparent revolutionary change in first-silicon trends: where an average of ~30% of designs claimed first silicon success over at least a decade, this metric has been dropping, with the latest survey now showing 5%. The analysis notes that silicon respins are expensive and risk missing market windows, and Foster breaks the trend down into 5 primary factors, including growing accelerator-based volumes (coherency issues in AI/GPU and CPU cluster designs), the increasingly intimate link between software and hardware, a changing verification language mix (System Verilog now neck and neck with C/C++ and Python, with PSS growing fast), and significant survey-reported growth in respins around firmware, safety and security. Foster does not see the language mix as a contributor to the low success rate, viewing it instead as a signal of how verification teams are responding to complexity.

Impact and signal

Affected components and suppliers

Source and time

Source: SemiWiki · 10/7/2026 · View original source