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Predicting Post-Route PPA from Macro and Standard-Cell Placements (U. of Alberta)
What happened
Researchers at the University of Alberta introduced "PPAPlace," a new chip placement optimization method. The study reveals that standard metrics like Half-Perimeter Wirelength (HPWL) have near-zero correlation with post-route timing. This technical advancement represents a shift in design methodology but currently has no direct impact on supply chain pricing or availability.
Impact and signal
Low impactImpact score: 5/100
Affected components and suppliers
R&DEDAPlacementPPA
Source and time
Source: Semiconductor Engineering · 8/29/2026 · View original source
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