Moving Beyond AI-Assisted Design – Agentrys Shows the Way with Agentic Loop Engineering

What happened

Agentrys published a case study stating that, using agentic loop engineering and its Agentrys Studio Platform, it autonomously optimized XiangShan, a Linux-class RISC-V processor: in eight hours the workflow found a configuration that, relative to an expert-tuned reference design, improved throughput by 40% while reducing power by 28% and area by 10%, and satisfied a 1.5 GHz timing objective the reference configuration could not meet; another configuration achieved approximately 0.84 W power consumption and 0.134 mm² area at 1.5 GHz. The workflow used compilation, correctness checking, cycle-accurate simulation, synthesis, physical implementation, and timing and power analysis, with approximately 50 physical evaluations; candidates that failed required checks were rejected. The XiangShan design contained approximately 143,000 lines of Chisel code across 528 source files, with 3,284 adjustable parameters organized into 17 microarchitectural subsystems; the primary benchmark was GAP BFS, a graph-processing workload in which approximately 88% of execution cycles were spent stalled on memory. As background, the article notes that at Hot Chips 2026 OpenAI presented Jalapeño, an inference ASIC built with AI in the design loop, reporting measured block-level wins over a human baseline — 56% on a BF16 multiply, alongside a 10% smaller matrix-unit area — within a roughly nine-month path from RTL to tapeout. These AI-driven optimization results are case-study reports with no direct link to chip prices or supply.

Impact and signal

Affected components and suppliers

Source and time

Source: SemiWiki · 10/19/2026 · View original source