[News] TSMC Touts Unmatched 5x Reticle-Size Packaging Prowess and High Yields, Ready to Step In if Rivals Fall Short

What happened

Reported on October 15, 2026: TSMC CEO C.C. Wei highlighted the company's ability to mass-produce 5x reticle-size packaging with strong yields, a feat he says rivals have yet to match, and signaled TSMC could step in if rival providers, including Intel's EMIB, struggle to meet customer demand. TSMC is doubling down on advanced packaging despite its own CoWoS capacity constraints, with 9x solutions under development and 14x on the horizon. According to an Anue report in August, TSMC Vice President of Advanced Packaging Technology and Service Jun He said the company's 5.5x reticle-size CoWoS technology has already entered high-volume production, with yields exceeding 98% for multiple AI customers and reaching as high as 99% for some; advancing one generation per year, TSMC expects to scale up to 14x reticle-size packaging by 2029, according to Anue. Wei also reportedly expects the next-generation A14 (1.4nm-class) process to become larger than N2 on stronger customer engagement, slated for risk production in 2027 and high-volume manufacturing in 2028. Intel is reportedly accelerating its 14A roadmap: CEO Lip-Bu Tan is reportedly targeting risk production as early as 1Q27, while Intel's official timeline remains more conservative, with internal 14A products planned for 2H27 and high-volume manufacturing in 2028. According to a July TechPowerUp report citing KeyBanc, Intel reportedly plans to manufacture 80–90% of its upcoming Nova Lake compute tiles internally, reversing an earlier dual-source strategy under which TSMC's N2 process was expected to handle 60–70% and Intel's 18A the rest. Wei stressed that the foundry treats all customers equally, whether IDMs or fabless designers, while factoring their internal manufacturing capacity into its own capacity planning.

Impact and signal

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Source and time

Source: TrendForce · 10/14/2026 · View original source