​SK Hynix Unveils H-TPU Controller Architecture with Over 100 Small Processors

What happened

At ISOCC 2026, held at Songdo Convensia in Incheon on Oct. 12, SK Hynix Vice President Koo In-je disclosed the architecture and performance of the Hynix Transaction Processing Unit (H-TPU), a small in-house-developed processor for solid-state drives (SSDs). The technology distributes repetitive tasks traditionally handled by general-purpose CPUs across more than 100 H-TPUs processed in parallel; according to SK Hynix, a single H-TPU consumes approximately 2.5% (one-fortieth) of the power and occupies about 4% (one-twenty-fifth) of the chip area compared to a standard general-purpose CPU core, while the main general-purpose CPU is reserved for complex tasks such as error recovery, exception handling, and storage policy management. The company has also developed software tools, including a dedicated compiler. SK Hynix plans to apply the H-TPU technology across multiple NAND flash product lines, starting with controllers for next-generation enterprise SSDs (eSSDs), then integrating it into Storage Next, its next-generation storage architecture for AI that handles data units down to 512 bytes—one-eighth the size of conventional 4KB units—as well as high-bandwidth flash (HBF), which is scheduled for release next year; these deployments remain plans and are not stated as implemented.

Impact and signal

Affected components and suppliers

Source and time

Source: The Elec · 10/12/2026 · View original source