NuAxiSemiconductor trade intelligence
Samsung pushes vertical transistor design as chip scaling hits limits
What happened
Samsung Electronics demonstrated a 3D stacked transistor structure with a 42-nanometer gate pitch, extending vertical integration from memory to logic semiconductors. This research milestone aims to address physical scaling limits in chip manufacturing. Currently, this has no direct impact on supply chain pricing or availability.
Impact and signal
Low impactImpact score: 10/100
Affected components and suppliers
Logic Semiconductors3D Stacked Transistors
R&D3D StackingTechnology
Source and time
Source: DigiTimes Asia · 6/17/2026 · View original source
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