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ISSCC: Electro-optical router in a chiplet package

What happened

CEA-Leti and CEA-List presented an electro-optical router chiplet at ISSCC, achieving 3.19pJ/bit efficiency and 18ns optical path setup. This R&D milestone enables dynamic, low-latency optical networking within chiplet packages for future HPC and AI systems. Neutral: This is a long-term R&D development with no immediate impact on component supply, demand, or pricing.

Impact and signal

Low impactImpact score: 10/100

Affected components and suppliers

Silicon PhotonicsOptical InterconnectChiplet Interposer
CEA-LetiCEA-List
R&DHPCAI AcceleratorsPackaging

Source and time

Source: Electronics Weekly · 2/18/2026 · View original source

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