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FPGA IP accelerates deterministic networking

What happened

Orthogone Technologies' Ultra-Low-Latency (ULL) FPGA IP Portfolio comprises production-ready networking and data-movement IP cores for AMD UltraScale+ and Versal adaptive platforms, and is available now for evaluation and licensing on AMD adaptive platforms. The portfolio combines Ethernet MAC/PCS with optional Reed-Solomon FEC, hardware TCP/IP and UDP/IP offload engines, and a PCIe circular-buffer DMA controller for deterministic, sub-microsecond-class networking and packet processing; the Ethernet MAC/PCS cores provide standards-compliant IEEE 802.3 Ethernet at 1G, 10G, 25G, 40G, and 100G line rates, with optional RS-FEC at 25G and 100G. The TCP/IP and UDP/IP offload engines handle Layer 2 through Layer 4 processing in FPGA logic, and the DMA controller enables bidirectional data movement between the host and FPGA over PCIe Gen3/Gen4. Early adopters are using the cores in aerospace, defense, and quantum computing applications.

Impact and signal

Low impactImpact score: 10/100

Affected components and suppliers

Ethernet MAC/PCS coresRS-FECTCP/IP offload engineUDP/IP offload enginePCIe circular-buffer DMA controllerUltra-Low-Latency (ULL) FPGA IP Portfolio
Orthogone TechnologiesAMD
FPGA IPdeterministic networkinglow latencyAMD UltraScale+AMD VersalEthernet MAC/PCS

Source and time

Source: EDN · 10/7/2026 · View original source

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