NuAxiSemiconductor trade intelligence

Configurable xSPI memory controller IP core is FuSa-ready

What happened

CAST introduces a configurable xSPI-MC IP core supporting HyperBus and Xccela interfaces with functional safety features, addressing protocol fragmentation.

Impact and signal

Low impactImpact score: 10/100

Affected components and suppliers

xSPIHyperBusXccelaSerial FlashSerial PSRAM

CASTCypressMicron

product_launchip_corexspi

Source and time

Source: SemiWiki · 5/13/2026 · View original source

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Configurable xSPI memory controller IP core is FuSa-ready

What happened

Impact and signal

Affected components and suppliers

Source and time

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